1*4882a593Smuzhiyun /***********************license start***************
2*4882a593Smuzhiyun * Author: Cavium Networks
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Contact: support@caviumnetworks.com
5*4882a593Smuzhiyun * This file is part of the OCTEON SDK
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2003-2008 Cavium Networks
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This file is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of the GNU General Public License, Version 2, as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This file is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16*4882a593Smuzhiyun * NONINFRINGEMENT. See the GNU General Public License for more
17*4882a593Smuzhiyun * details.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
20*4882a593Smuzhiyun * along with this file; if not, write to the Free Software
21*4882a593Smuzhiyun * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22*4882a593Smuzhiyun * or visit http://www.gnu.org/licenses/.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * This file may also be available under a different license from Cavium.
25*4882a593Smuzhiyun * Contact Cavium Networks for more information
26*4882a593Smuzhiyun ***********************license end**************************************/
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Small helper utilities.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun #include <linux/kernel.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <asm/octeon/cvmx-config.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include <asm/octeon/cvmx-fpa.h>
38*4882a593Smuzhiyun #include <asm/octeon/cvmx-pip.h>
39*4882a593Smuzhiyun #include <asm/octeon/cvmx-pko.h>
40*4882a593Smuzhiyun #include <asm/octeon/cvmx-ipd.h>
41*4882a593Smuzhiyun #include <asm/octeon/cvmx-spi.h>
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #include <asm/octeon/cvmx-helper.h>
44*4882a593Smuzhiyun #include <asm/octeon/cvmx-helper-util.h>
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #include <asm/octeon/cvmx-ipd-defs.h>
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun * Convert a interface mode into a human readable string
50*4882a593Smuzhiyun *
51*4882a593Smuzhiyun * @mode: Mode to convert
52*4882a593Smuzhiyun *
53*4882a593Smuzhiyun * Returns String
54*4882a593Smuzhiyun */
cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode)55*4882a593Smuzhiyun const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
56*4882a593Smuzhiyun mode)
57*4882a593Smuzhiyun {
58*4882a593Smuzhiyun switch (mode) {
59*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_DISABLED:
60*4882a593Smuzhiyun return "DISABLED";
61*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_RGMII:
62*4882a593Smuzhiyun return "RGMII";
63*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_GMII:
64*4882a593Smuzhiyun return "GMII";
65*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_SPI:
66*4882a593Smuzhiyun return "SPI";
67*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_PCIE:
68*4882a593Smuzhiyun return "PCIE";
69*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_XAUI:
70*4882a593Smuzhiyun return "XAUI";
71*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_SGMII:
72*4882a593Smuzhiyun return "SGMII";
73*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_PICMG:
74*4882a593Smuzhiyun return "PICMG";
75*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_NPI:
76*4882a593Smuzhiyun return "NPI";
77*4882a593Smuzhiyun case CVMX_HELPER_INTERFACE_MODE_LOOP:
78*4882a593Smuzhiyun return "LOOP";
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun return "UNKNOWN";
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /**
84*4882a593Smuzhiyun * Setup Random Early Drop on a specific input queue
85*4882a593Smuzhiyun *
86*4882a593Smuzhiyun * @queue: Input queue to setup RED on (0-7)
87*4882a593Smuzhiyun * @pass_thresh:
88*4882a593Smuzhiyun * Packets will begin slowly dropping when there are less than
89*4882a593Smuzhiyun * this many packet buffers free in FPA 0.
90*4882a593Smuzhiyun * @drop_thresh:
91*4882a593Smuzhiyun * All incoming packets will be dropped when there are less
92*4882a593Smuzhiyun * than this many free packet buffers in FPA 0.
93*4882a593Smuzhiyun * Returns Zero on success. Negative on failure
94*4882a593Smuzhiyun */
cvmx_helper_setup_red_queue(int queue,int pass_thresh,int drop_thresh)95*4882a593Smuzhiyun static int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
96*4882a593Smuzhiyun int drop_thresh)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun union cvmx_ipd_qosx_red_marks red_marks;
99*4882a593Smuzhiyun union cvmx_ipd_red_quex_param red_param;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Set RED to begin dropping packets when there are pass_thresh buffers
102*4882a593Smuzhiyun left. It will linearly drop more packets until reaching drop_thresh
103*4882a593Smuzhiyun buffers */
104*4882a593Smuzhiyun red_marks.u64 = 0;
105*4882a593Smuzhiyun red_marks.s.drop = drop_thresh;
106*4882a593Smuzhiyun red_marks.s.pass = pass_thresh;
107*4882a593Smuzhiyun cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /* Use the actual queue 0 counter, not the average */
110*4882a593Smuzhiyun red_param.u64 = 0;
111*4882a593Smuzhiyun red_param.s.prb_con =
112*4882a593Smuzhiyun (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
113*4882a593Smuzhiyun red_param.s.avg_con = 1;
114*4882a593Smuzhiyun red_param.s.new_con = 255;
115*4882a593Smuzhiyun red_param.s.use_pcnt = 1;
116*4882a593Smuzhiyun cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
117*4882a593Smuzhiyun return 0;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /**
121*4882a593Smuzhiyun * Setup Random Early Drop to automatically begin dropping packets.
122*4882a593Smuzhiyun *
123*4882a593Smuzhiyun * @pass_thresh:
124*4882a593Smuzhiyun * Packets will begin slowly dropping when there are less than
125*4882a593Smuzhiyun * this many packet buffers free in FPA 0.
126*4882a593Smuzhiyun * @drop_thresh:
127*4882a593Smuzhiyun * All incoming packets will be dropped when there are less
128*4882a593Smuzhiyun * than this many free packet buffers in FPA 0.
129*4882a593Smuzhiyun * Returns Zero on success. Negative on failure
130*4882a593Smuzhiyun */
cvmx_helper_setup_red(int pass_thresh,int drop_thresh)131*4882a593Smuzhiyun int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun union cvmx_ipd_portx_bp_page_cnt page_cnt;
134*4882a593Smuzhiyun union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end;
135*4882a593Smuzhiyun union cvmx_ipd_red_port_enable red_port_enable;
136*4882a593Smuzhiyun int queue;
137*4882a593Smuzhiyun int interface;
138*4882a593Smuzhiyun int port;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* Disable backpressure based on queued buffers. It needs SW support */
141*4882a593Smuzhiyun page_cnt.u64 = 0;
142*4882a593Smuzhiyun page_cnt.s.bp_enb = 0;
143*4882a593Smuzhiyun page_cnt.s.page_cnt = 100;
144*4882a593Smuzhiyun for (interface = 0; interface < 2; interface++) {
145*4882a593Smuzhiyun for (port = cvmx_helper_get_first_ipd_port(interface);
146*4882a593Smuzhiyun port < cvmx_helper_get_last_ipd_port(interface); port++)
147*4882a593Smuzhiyun cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
148*4882a593Smuzhiyun page_cnt.u64);
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun for (queue = 0; queue < 8; queue++)
152*4882a593Smuzhiyun cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /* Shutoff the dropping based on the per port page count. SW isn't
155*4882a593Smuzhiyun decrementing it right now */
156*4882a593Smuzhiyun ipd_bp_prt_red_end.u64 = 0;
157*4882a593Smuzhiyun ipd_bp_prt_red_end.s.prt_enb = 0;
158*4882a593Smuzhiyun cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun red_port_enable.u64 = 0;
161*4882a593Smuzhiyun red_port_enable.s.prt_enb = 0xfffffffffull;
162*4882a593Smuzhiyun red_port_enable.s.avg_dly = 10000;
163*4882a593Smuzhiyun red_port_enable.s.prb_dly = 10000;
164*4882a593Smuzhiyun cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return 0;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cvmx_helper_setup_red);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /**
171*4882a593Smuzhiyun * Setup the common GMX settings that determine the number of
172*4882a593Smuzhiyun * ports. These setting apply to almost all configurations of all
173*4882a593Smuzhiyun * chips.
174*4882a593Smuzhiyun *
175*4882a593Smuzhiyun * @interface: Interface to configure
176*4882a593Smuzhiyun * @num_ports: Number of ports on the interface
177*4882a593Smuzhiyun *
178*4882a593Smuzhiyun * Returns Zero on success, negative on failure
179*4882a593Smuzhiyun */
__cvmx_helper_setup_gmx(int interface,int num_ports)180*4882a593Smuzhiyun int __cvmx_helper_setup_gmx(int interface, int num_ports)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun union cvmx_gmxx_tx_prts gmx_tx_prts;
183*4882a593Smuzhiyun union cvmx_gmxx_rx_prts gmx_rx_prts;
184*4882a593Smuzhiyun union cvmx_pko_reg_gmx_port_mode pko_mode;
185*4882a593Smuzhiyun union cvmx_gmxx_txx_thresh gmx_tx_thresh;
186*4882a593Smuzhiyun int index;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /* Tell GMX the number of TX ports on this interface */
189*4882a593Smuzhiyun gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
190*4882a593Smuzhiyun gmx_tx_prts.s.prts = num_ports;
191*4882a593Smuzhiyun cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* Tell GMX the number of RX ports on this interface. This only
194*4882a593Smuzhiyun ** applies to *GMII and XAUI ports */
195*4882a593Smuzhiyun if (cvmx_helper_interface_get_mode(interface) ==
196*4882a593Smuzhiyun CVMX_HELPER_INTERFACE_MODE_RGMII
197*4882a593Smuzhiyun || cvmx_helper_interface_get_mode(interface) ==
198*4882a593Smuzhiyun CVMX_HELPER_INTERFACE_MODE_SGMII
199*4882a593Smuzhiyun || cvmx_helper_interface_get_mode(interface) ==
200*4882a593Smuzhiyun CVMX_HELPER_INTERFACE_MODE_GMII
201*4882a593Smuzhiyun || cvmx_helper_interface_get_mode(interface) ==
202*4882a593Smuzhiyun CVMX_HELPER_INTERFACE_MODE_XAUI) {
203*4882a593Smuzhiyun if (num_ports > 4) {
204*4882a593Smuzhiyun cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal "
205*4882a593Smuzhiyun "num_ports\n");
206*4882a593Smuzhiyun return -1;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
210*4882a593Smuzhiyun gmx_rx_prts.s.prts = num_ports;
211*4882a593Smuzhiyun cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */
215*4882a593Smuzhiyun if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX)
216*4882a593Smuzhiyun && !OCTEON_IS_MODEL(OCTEON_CN50XX)) {
217*4882a593Smuzhiyun /* Tell PKO the number of ports on this interface */
218*4882a593Smuzhiyun pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
219*4882a593Smuzhiyun if (interface == 0) {
220*4882a593Smuzhiyun if (num_ports == 1)
221*4882a593Smuzhiyun pko_mode.s.mode0 = 4;
222*4882a593Smuzhiyun else if (num_ports == 2)
223*4882a593Smuzhiyun pko_mode.s.mode0 = 3;
224*4882a593Smuzhiyun else if (num_ports <= 4)
225*4882a593Smuzhiyun pko_mode.s.mode0 = 2;
226*4882a593Smuzhiyun else if (num_ports <= 8)
227*4882a593Smuzhiyun pko_mode.s.mode0 = 1;
228*4882a593Smuzhiyun else
229*4882a593Smuzhiyun pko_mode.s.mode0 = 0;
230*4882a593Smuzhiyun } else {
231*4882a593Smuzhiyun if (num_ports == 1)
232*4882a593Smuzhiyun pko_mode.s.mode1 = 4;
233*4882a593Smuzhiyun else if (num_ports == 2)
234*4882a593Smuzhiyun pko_mode.s.mode1 = 3;
235*4882a593Smuzhiyun else if (num_ports <= 4)
236*4882a593Smuzhiyun pko_mode.s.mode1 = 2;
237*4882a593Smuzhiyun else if (num_ports <= 8)
238*4882a593Smuzhiyun pko_mode.s.mode1 = 1;
239*4882a593Smuzhiyun else
240*4882a593Smuzhiyun pko_mode.s.mode1 = 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /*
246*4882a593Smuzhiyun * Set GMX to buffer as much data as possible before starting
247*4882a593Smuzhiyun * transmit. This reduces the chances that we have a TX under
248*4882a593Smuzhiyun * run due to memory contention. Any packet that fits entirely
249*4882a593Smuzhiyun * in the GMX FIFO can never have an under run regardless of
250*4882a593Smuzhiyun * memory load.
251*4882a593Smuzhiyun */
252*4882a593Smuzhiyun gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface));
253*4882a593Smuzhiyun if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
254*4882a593Smuzhiyun || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
255*4882a593Smuzhiyun /* These chips have a fixed max threshold of 0x40 */
256*4882a593Smuzhiyun gmx_tx_thresh.s.cnt = 0x40;
257*4882a593Smuzhiyun } else {
258*4882a593Smuzhiyun /* Choose the max value for the number of ports */
259*4882a593Smuzhiyun if (num_ports <= 1)
260*4882a593Smuzhiyun gmx_tx_thresh.s.cnt = 0x100 / 1;
261*4882a593Smuzhiyun else if (num_ports == 2)
262*4882a593Smuzhiyun gmx_tx_thresh.s.cnt = 0x100 / 2;
263*4882a593Smuzhiyun else
264*4882a593Smuzhiyun gmx_tx_thresh.s.cnt = 0x100 / 4;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun /*
267*4882a593Smuzhiyun * SPI and XAUI can have lots of ports but the GMX hardware
268*4882a593Smuzhiyun * only ever has a max of 4.
269*4882a593Smuzhiyun */
270*4882a593Smuzhiyun if (num_ports > 4)
271*4882a593Smuzhiyun num_ports = 4;
272*4882a593Smuzhiyun for (index = 0; index < num_ports; index++)
273*4882a593Smuzhiyun cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface),
274*4882a593Smuzhiyun gmx_tx_thresh.u64);
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun return 0;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun /**
280*4882a593Smuzhiyun * Returns the IPD/PKO port number for a port on the given
281*4882a593Smuzhiyun * interface.
282*4882a593Smuzhiyun *
283*4882a593Smuzhiyun * @interface: Interface to use
284*4882a593Smuzhiyun * @port: Port on the interface
285*4882a593Smuzhiyun *
286*4882a593Smuzhiyun * Returns IPD/PKO port number
287*4882a593Smuzhiyun */
cvmx_helper_get_ipd_port(int interface,int port)288*4882a593Smuzhiyun int cvmx_helper_get_ipd_port(int interface, int port)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun switch (interface) {
291*4882a593Smuzhiyun case 0:
292*4882a593Smuzhiyun return port;
293*4882a593Smuzhiyun case 1:
294*4882a593Smuzhiyun return port + 16;
295*4882a593Smuzhiyun case 2:
296*4882a593Smuzhiyun return port + 32;
297*4882a593Smuzhiyun case 3:
298*4882a593Smuzhiyun return port + 36;
299*4882a593Smuzhiyun case 4:
300*4882a593Smuzhiyun return port + 40;
301*4882a593Smuzhiyun case 5:
302*4882a593Smuzhiyun return port + 44;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun return -1;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cvmx_helper_get_ipd_port);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /**
309*4882a593Smuzhiyun * Returns the interface number for an IPD/PKO port number.
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * @ipd_port: IPD/PKO port number
312*4882a593Smuzhiyun *
313*4882a593Smuzhiyun * Returns Interface number
314*4882a593Smuzhiyun */
cvmx_helper_get_interface_num(int ipd_port)315*4882a593Smuzhiyun int cvmx_helper_get_interface_num(int ipd_port)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun if (ipd_port < 16)
318*4882a593Smuzhiyun return 0;
319*4882a593Smuzhiyun else if (ipd_port < 32)
320*4882a593Smuzhiyun return 1;
321*4882a593Smuzhiyun else if (ipd_port < 36)
322*4882a593Smuzhiyun return 2;
323*4882a593Smuzhiyun else if (ipd_port < 40)
324*4882a593Smuzhiyun return 3;
325*4882a593Smuzhiyun else if (ipd_port < 44)
326*4882a593Smuzhiyun return 4;
327*4882a593Smuzhiyun else if (ipd_port < 48)
328*4882a593Smuzhiyun return 5;
329*4882a593Smuzhiyun else
330*4882a593Smuzhiyun cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD "
331*4882a593Smuzhiyun "port number\n");
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun return -1;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_num);
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /**
338*4882a593Smuzhiyun * Returns the interface index number for an IPD/PKO port
339*4882a593Smuzhiyun * number.
340*4882a593Smuzhiyun *
341*4882a593Smuzhiyun * @ipd_port: IPD/PKO port number
342*4882a593Smuzhiyun *
343*4882a593Smuzhiyun * Returns Interface index number
344*4882a593Smuzhiyun */
cvmx_helper_get_interface_index_num(int ipd_port)345*4882a593Smuzhiyun int cvmx_helper_get_interface_index_num(int ipd_port)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun if (ipd_port < 32)
348*4882a593Smuzhiyun return ipd_port & 15;
349*4882a593Smuzhiyun else if (ipd_port < 36)
350*4882a593Smuzhiyun return ipd_port & 3;
351*4882a593Smuzhiyun else if (ipd_port < 40)
352*4882a593Smuzhiyun return ipd_port & 3;
353*4882a593Smuzhiyun else if (ipd_port < 44)
354*4882a593Smuzhiyun return ipd_port & 3;
355*4882a593Smuzhiyun else if (ipd_port < 48)
356*4882a593Smuzhiyun return ipd_port & 3;
357*4882a593Smuzhiyun else
358*4882a593Smuzhiyun cvmx_dprintf("cvmx_helper_get_interface_index_num: "
359*4882a593Smuzhiyun "Illegal IPD port number\n");
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun return -1;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(cvmx_helper_get_interface_index_num);
364