xref: /OK3568_Linux_fs/kernel/arch/mips/cavium-octeon/dma-octeon.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun  * License.  See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun  * for more details.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
7*4882a593Smuzhiyun  * Copyright (C) 2000, 2001  Ralf Baechle <ralf@gnu.org>
8*4882a593Smuzhiyun  * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
9*4882a593Smuzhiyun  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
10*4882a593Smuzhiyun  * IP32 changes by Ilya.
11*4882a593Smuzhiyun  * Copyright (C) 2010 Cavium Networks, Inc.
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun #include <linux/dma-direct.h>
14*4882a593Smuzhiyun #include <linux/memblock.h>
15*4882a593Smuzhiyun #include <linux/swiotlb.h>
16*4882a593Smuzhiyun #include <linux/types.h>
17*4882a593Smuzhiyun #include <linux/init.h>
18*4882a593Smuzhiyun #include <linux/mm.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include <asm/bootinfo.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <asm/octeon/octeon.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #ifdef CONFIG_PCI
25*4882a593Smuzhiyun #include <linux/pci.h>
26*4882a593Smuzhiyun #include <asm/octeon/pci-octeon.h>
27*4882a593Smuzhiyun #include <asm/octeon/cvmx-npi-defs.h>
28*4882a593Smuzhiyun #include <asm/octeon/cvmx-pci-defs.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct octeon_dma_map_ops {
31*4882a593Smuzhiyun 	dma_addr_t (*phys_to_dma)(struct device *dev, phys_addr_t paddr);
32*4882a593Smuzhiyun 	phys_addr_t (*dma_to_phys)(struct device *dev, dma_addr_t daddr);
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
octeon_hole_phys_to_dma(phys_addr_t paddr)35*4882a593Smuzhiyun static dma_addr_t octeon_hole_phys_to_dma(phys_addr_t paddr)
36*4882a593Smuzhiyun {
37*4882a593Smuzhiyun 	if (paddr >= CVMX_PCIE_BAR1_PHYS_BASE && paddr < (CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_PHYS_SIZE))
38*4882a593Smuzhiyun 		return paddr - CVMX_PCIE_BAR1_PHYS_BASE + CVMX_PCIE_BAR1_RC_BASE;
39*4882a593Smuzhiyun 	else
40*4882a593Smuzhiyun 		return paddr;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun 
octeon_hole_dma_to_phys(dma_addr_t daddr)43*4882a593Smuzhiyun static phys_addr_t octeon_hole_dma_to_phys(dma_addr_t daddr)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	if (daddr >= CVMX_PCIE_BAR1_RC_BASE)
46*4882a593Smuzhiyun 		return daddr + CVMX_PCIE_BAR1_PHYS_BASE - CVMX_PCIE_BAR1_RC_BASE;
47*4882a593Smuzhiyun 	else
48*4882a593Smuzhiyun 		return daddr;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
octeon_gen1_phys_to_dma(struct device * dev,phys_addr_t paddr)51*4882a593Smuzhiyun static dma_addr_t octeon_gen1_phys_to_dma(struct device *dev, phys_addr_t paddr)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
54*4882a593Smuzhiyun 		paddr -= 0x400000000ull;
55*4882a593Smuzhiyun 	return octeon_hole_phys_to_dma(paddr);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
octeon_gen1_dma_to_phys(struct device * dev,dma_addr_t daddr)58*4882a593Smuzhiyun static phys_addr_t octeon_gen1_dma_to_phys(struct device *dev, dma_addr_t daddr)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	daddr = octeon_hole_dma_to_phys(daddr);
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
63*4882a593Smuzhiyun 		daddr += 0x400000000ull;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	return daddr;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun static const struct octeon_dma_map_ops octeon_gen1_ops = {
69*4882a593Smuzhiyun 	.phys_to_dma	= octeon_gen1_phys_to_dma,
70*4882a593Smuzhiyun 	.dma_to_phys	= octeon_gen1_dma_to_phys,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
octeon_gen2_phys_to_dma(struct device * dev,phys_addr_t paddr)73*4882a593Smuzhiyun static dma_addr_t octeon_gen2_phys_to_dma(struct device *dev, phys_addr_t paddr)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	return octeon_hole_phys_to_dma(paddr);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun 
octeon_gen2_dma_to_phys(struct device * dev,dma_addr_t daddr)78*4882a593Smuzhiyun static phys_addr_t octeon_gen2_dma_to_phys(struct device *dev, dma_addr_t daddr)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun 	return octeon_hole_dma_to_phys(daddr);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun static const struct octeon_dma_map_ops octeon_gen2_ops = {
84*4882a593Smuzhiyun 	.phys_to_dma	= octeon_gen2_phys_to_dma,
85*4882a593Smuzhiyun 	.dma_to_phys	= octeon_gen2_dma_to_phys,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
octeon_big_phys_to_dma(struct device * dev,phys_addr_t paddr)88*4882a593Smuzhiyun static dma_addr_t octeon_big_phys_to_dma(struct device *dev, phys_addr_t paddr)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
91*4882a593Smuzhiyun 		paddr -= 0x400000000ull;
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	/* Anything in the BAR1 hole or above goes via BAR2 */
94*4882a593Smuzhiyun 	if (paddr >= 0xf0000000ull)
95*4882a593Smuzhiyun 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	return paddr;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun 
octeon_big_dma_to_phys(struct device * dev,dma_addr_t daddr)100*4882a593Smuzhiyun static phys_addr_t octeon_big_dma_to_phys(struct device *dev, dma_addr_t daddr)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
103*4882a593Smuzhiyun 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
106*4882a593Smuzhiyun 		daddr += 0x400000000ull;
107*4882a593Smuzhiyun 	return daddr;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const struct octeon_dma_map_ops octeon_big_ops = {
111*4882a593Smuzhiyun 	.phys_to_dma	= octeon_big_phys_to_dma,
112*4882a593Smuzhiyun 	.dma_to_phys	= octeon_big_dma_to_phys,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
octeon_small_phys_to_dma(struct device * dev,phys_addr_t paddr)115*4882a593Smuzhiyun static dma_addr_t octeon_small_phys_to_dma(struct device *dev,
116*4882a593Smuzhiyun 					   phys_addr_t paddr)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun 	if (paddr >= 0x410000000ull && paddr < 0x420000000ull)
119*4882a593Smuzhiyun 		paddr -= 0x400000000ull;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/* Anything not in the BAR1 range goes via BAR2 */
122*4882a593Smuzhiyun 	if (paddr >= octeon_bar1_pci_phys && paddr < octeon_bar1_pci_phys + 0x8000000ull)
123*4882a593Smuzhiyun 		paddr = paddr - octeon_bar1_pci_phys;
124*4882a593Smuzhiyun 	else
125*4882a593Smuzhiyun 		paddr = OCTEON_BAR2_PCI_ADDRESS + paddr;
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	return paddr;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
octeon_small_dma_to_phys(struct device * dev,dma_addr_t daddr)130*4882a593Smuzhiyun static phys_addr_t octeon_small_dma_to_phys(struct device *dev,
131*4882a593Smuzhiyun 					    dma_addr_t daddr)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun 	if (daddr >= OCTEON_BAR2_PCI_ADDRESS)
134*4882a593Smuzhiyun 		daddr -= OCTEON_BAR2_PCI_ADDRESS;
135*4882a593Smuzhiyun 	else
136*4882a593Smuzhiyun 		daddr += octeon_bar1_pci_phys;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	if (daddr >= 0x10000000ull && daddr < 0x20000000ull)
139*4882a593Smuzhiyun 		daddr += 0x400000000ull;
140*4882a593Smuzhiyun 	return daddr;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const struct octeon_dma_map_ops octeon_small_ops = {
144*4882a593Smuzhiyun 	.phys_to_dma	= octeon_small_phys_to_dma,
145*4882a593Smuzhiyun 	.dma_to_phys	= octeon_small_dma_to_phys,
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun static const struct octeon_dma_map_ops *octeon_pci_dma_ops;
149*4882a593Smuzhiyun 
octeon_pci_dma_init(void)150*4882a593Smuzhiyun void __init octeon_pci_dma_init(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	switch (octeon_dma_bar_type) {
153*4882a593Smuzhiyun 	case OCTEON_DMA_BAR_TYPE_PCIE:
154*4882a593Smuzhiyun 		octeon_pci_dma_ops = &octeon_gen1_ops;
155*4882a593Smuzhiyun 		break;
156*4882a593Smuzhiyun 	case OCTEON_DMA_BAR_TYPE_PCIE2:
157*4882a593Smuzhiyun 		octeon_pci_dma_ops = &octeon_gen2_ops;
158*4882a593Smuzhiyun 		break;
159*4882a593Smuzhiyun 	case OCTEON_DMA_BAR_TYPE_BIG:
160*4882a593Smuzhiyun 		octeon_pci_dma_ops = &octeon_big_ops;
161*4882a593Smuzhiyun 		break;
162*4882a593Smuzhiyun 	case OCTEON_DMA_BAR_TYPE_SMALL:
163*4882a593Smuzhiyun 		octeon_pci_dma_ops = &octeon_small_ops;
164*4882a593Smuzhiyun 		break;
165*4882a593Smuzhiyun 	default:
166*4882a593Smuzhiyun 		BUG();
167*4882a593Smuzhiyun 	}
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun #endif /* CONFIG_PCI */
170*4882a593Smuzhiyun 
phys_to_dma(struct device * dev,phys_addr_t paddr)171*4882a593Smuzhiyun dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun #ifdef CONFIG_PCI
174*4882a593Smuzhiyun 	if (dev && dev_is_pci(dev))
175*4882a593Smuzhiyun 		return octeon_pci_dma_ops->phys_to_dma(dev, paddr);
176*4882a593Smuzhiyun #endif
177*4882a593Smuzhiyun 	return paddr;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
dma_to_phys(struct device * dev,dma_addr_t daddr)180*4882a593Smuzhiyun phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun #ifdef CONFIG_PCI
183*4882a593Smuzhiyun 	if (dev && dev_is_pci(dev))
184*4882a593Smuzhiyun 		return octeon_pci_dma_ops->dma_to_phys(dev, daddr);
185*4882a593Smuzhiyun #endif
186*4882a593Smuzhiyun 	return daddr;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun char *octeon_swiotlb;
190*4882a593Smuzhiyun 
plat_swiotlb_setup(void)191*4882a593Smuzhiyun void __init plat_swiotlb_setup(void)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	phys_addr_t start, end;
194*4882a593Smuzhiyun 	phys_addr_t max_addr;
195*4882a593Smuzhiyun 	phys_addr_t addr_size;
196*4882a593Smuzhiyun 	size_t swiotlbsize;
197*4882a593Smuzhiyun 	unsigned long swiotlb_nslabs;
198*4882a593Smuzhiyun 	u64 i;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	max_addr = 0;
201*4882a593Smuzhiyun 	addr_size = 0;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 	for_each_mem_range(i, &start, &end) {
204*4882a593Smuzhiyun 		/* These addresses map low for PCI. */
205*4882a593Smuzhiyun 		if (start > 0x410000000ull && !OCTEON_IS_OCTEON2())
206*4882a593Smuzhiyun 			continue;
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 		addr_size += (end - start);
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 		if (max_addr < end)
211*4882a593Smuzhiyun 			max_addr = end;
212*4882a593Smuzhiyun 	}
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	swiotlbsize = PAGE_SIZE;
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun #ifdef CONFIG_PCI
217*4882a593Smuzhiyun 	/*
218*4882a593Smuzhiyun 	 * For OCTEON_DMA_BAR_TYPE_SMALL, size the iotlb at 1/4 memory
219*4882a593Smuzhiyun 	 * size to a maximum of 64MB
220*4882a593Smuzhiyun 	 */
221*4882a593Smuzhiyun 	if (OCTEON_IS_MODEL(OCTEON_CN31XX)
222*4882a593Smuzhiyun 	    || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) {
223*4882a593Smuzhiyun 		swiotlbsize = addr_size / 4;
224*4882a593Smuzhiyun 		if (swiotlbsize > 64 * (1<<20))
225*4882a593Smuzhiyun 			swiotlbsize = 64 * (1<<20);
226*4882a593Smuzhiyun 	} else if (max_addr > 0xf0000000ul) {
227*4882a593Smuzhiyun 		/*
228*4882a593Smuzhiyun 		 * Otherwise only allocate a big iotlb if there is
229*4882a593Smuzhiyun 		 * memory past the BAR1 hole.
230*4882a593Smuzhiyun 		 */
231*4882a593Smuzhiyun 		swiotlbsize = 64 * (1<<20);
232*4882a593Smuzhiyun 	}
233*4882a593Smuzhiyun #endif
234*4882a593Smuzhiyun #ifdef CONFIG_USB_OHCI_HCD_PLATFORM
235*4882a593Smuzhiyun 	/* OCTEON II ohci is only 32-bit. */
236*4882a593Smuzhiyun 	if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul)
237*4882a593Smuzhiyun 		swiotlbsize = 64 * (1<<20);
238*4882a593Smuzhiyun #endif
239*4882a593Smuzhiyun 	swiotlb_nslabs = swiotlbsize >> IO_TLB_SHIFT;
240*4882a593Smuzhiyun 	swiotlb_nslabs = ALIGN(swiotlb_nslabs, IO_TLB_SEGSIZE);
241*4882a593Smuzhiyun 	swiotlbsize = swiotlb_nslabs << IO_TLB_SHIFT;
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	octeon_swiotlb = memblock_alloc_low(swiotlbsize, PAGE_SIZE);
244*4882a593Smuzhiyun 	if (!octeon_swiotlb)
245*4882a593Smuzhiyun 		panic("%s: Failed to allocate %zu bytes align=%lx\n",
246*4882a593Smuzhiyun 		      __func__, swiotlbsize, PAGE_SIZE);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	if (swiotlb_init_with_tbl(octeon_swiotlb, swiotlb_nslabs, 1) == -ENOMEM)
249*4882a593Smuzhiyun 		panic("Cannot allocate SWIOTLB buffer");
250*4882a593Smuzhiyun }
251