1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunif CPU_CAVIUM_OCTEON 3*4882a593Smuzhiyun 4*4882a593Smuzhiyunconfig CAVIUM_CN63XXP1 5*4882a593Smuzhiyun bool "Enable CN63XXP1 errata workarounds" 6*4882a593Smuzhiyun default "n" 7*4882a593Smuzhiyun help 8*4882a593Smuzhiyun The CN63XXP1 chip requires build time workarounds to 9*4882a593Smuzhiyun function reliably, select this option to enable them. These 10*4882a593Smuzhiyun workarounds will cause a slight decrease in performance on 11*4882a593Smuzhiyun non-CN63XXP1 hardware, so it is recommended to select "n" 12*4882a593Smuzhiyun unless it is known the workarounds are needed. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunconfig CAVIUM_OCTEON_CVMSEG_SIZE 15*4882a593Smuzhiyun int "Number of L1 cache lines reserved for CVMSEG memory" 16*4882a593Smuzhiyun range 0 54 17*4882a593Smuzhiyun default 1 18*4882a593Smuzhiyun help 19*4882a593Smuzhiyun CVMSEG LM is a segment that accesses portions of the dcache as a 20*4882a593Smuzhiyun local memory; the larger CVMSEG is, the smaller the cache is. 21*4882a593Smuzhiyun This selects the size of CVMSEG LM, which is in cache blocks. The 22*4882a593Smuzhiyun legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is 23*4882a593Smuzhiyun between zero and 6192 bytes). 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunendif # CPU_CAVIUM_OCTEON 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunif CAVIUM_OCTEON_SOC 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2 30*4882a593Smuzhiyun bool "Lock often used kernel code in the L2" 31*4882a593Smuzhiyun default "y" 32*4882a593Smuzhiyun help 33*4882a593Smuzhiyun Enable locking parts of the kernel into the L2 cache. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2_TLB 36*4882a593Smuzhiyun bool "Lock the TLB handler in L2" 37*4882a593Smuzhiyun depends on CAVIUM_OCTEON_LOCK_L2 38*4882a593Smuzhiyun default "y" 39*4882a593Smuzhiyun help 40*4882a593Smuzhiyun Lock the low level TLB fast path into L2. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2_EXCEPTION 43*4882a593Smuzhiyun bool "Lock the exception handler in L2" 44*4882a593Smuzhiyun depends on CAVIUM_OCTEON_LOCK_L2 45*4882a593Smuzhiyun default "y" 46*4882a593Smuzhiyun help 47*4882a593Smuzhiyun Lock the low level exception handler into L2. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT 50*4882a593Smuzhiyun bool "Lock the interrupt handler in L2" 51*4882a593Smuzhiyun depends on CAVIUM_OCTEON_LOCK_L2 52*4882a593Smuzhiyun default "y" 53*4882a593Smuzhiyun help 54*4882a593Smuzhiyun Lock the low level interrupt handler into L2. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2_INTERRUPT 57*4882a593Smuzhiyun bool "Lock the 2nd level interrupt handler in L2" 58*4882a593Smuzhiyun depends on CAVIUM_OCTEON_LOCK_L2 59*4882a593Smuzhiyun default "y" 60*4882a593Smuzhiyun help 61*4882a593Smuzhiyun Lock the 2nd level interrupt handler in L2. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunconfig CAVIUM_OCTEON_LOCK_L2_MEMCPY 64*4882a593Smuzhiyun bool "Lock memcpy() in L2" 65*4882a593Smuzhiyun depends on CAVIUM_OCTEON_LOCK_L2 66*4882a593Smuzhiyun default "y" 67*4882a593Smuzhiyun help 68*4882a593Smuzhiyun Lock the kernel's implementation of memcpy() into L2. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunconfig OCTEON_ILM 71*4882a593Smuzhiyun tristate "Module to measure interrupt latency using Octeon CIU Timer" 72*4882a593Smuzhiyun help 73*4882a593Smuzhiyun This driver is a module to measure interrupt latency using the 74*4882a593Smuzhiyun the CIU Timers on Octeon. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun To compile this driver as a module, choose M here. The module 77*4882a593Smuzhiyun will be called octeon-ilm 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunendif # CAVIUM_OCTEON_SOC 80