xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/ralink/mt7628a.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun/ {
4*4882a593Smuzhiyun	#address-cells = <1>;
5*4882a593Smuzhiyun	#size-cells = <1>;
6*4882a593Smuzhiyun	compatible = "ralink,mt7628a-soc";
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun	cpus {
9*4882a593Smuzhiyun		#address-cells = <1>;
10*4882a593Smuzhiyun		#size-cells = <0>;
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun		cpu@0 {
13*4882a593Smuzhiyun			compatible = "mti,mips24KEc";
14*4882a593Smuzhiyun			device_type = "cpu";
15*4882a593Smuzhiyun			reg = <0>;
16*4882a593Smuzhiyun		};
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	resetc: reset-controller {
20*4882a593Smuzhiyun		compatible = "ralink,rt2880-reset";
21*4882a593Smuzhiyun		#reset-cells = <1>;
22*4882a593Smuzhiyun	};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun	cpuintc: interrupt-controller {
25*4882a593Smuzhiyun		#address-cells = <0>;
26*4882a593Smuzhiyun		#interrupt-cells = <1>;
27*4882a593Smuzhiyun		interrupt-controller;
28*4882a593Smuzhiyun		compatible = "mti,cpu-interrupt-controller";
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	palmbus@10000000 {
32*4882a593Smuzhiyun		compatible = "palmbus";
33*4882a593Smuzhiyun		reg = <0x10000000 0x200000>;
34*4882a593Smuzhiyun		ranges = <0x0 0x10000000 0x1FFFFF>;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun		#address-cells = <1>;
37*4882a593Smuzhiyun		#size-cells = <1>;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun		sysc: system-controller@0 {
40*4882a593Smuzhiyun			compatible = "ralink,mt7620a-sysc", "syscon";
41*4882a593Smuzhiyun			reg = <0x0 0x60>;
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun		pinmux: pinmux@60 {
45*4882a593Smuzhiyun			compatible = "pinctrl-single";
46*4882a593Smuzhiyun			reg = <0x60 0x8>;
47*4882a593Smuzhiyun			#address-cells = <1>;
48*4882a593Smuzhiyun			#size-cells = <0>;
49*4882a593Smuzhiyun			#pinctrl-cells = <2>;
50*4882a593Smuzhiyun			pinctrl-single,bit-per-mux;
51*4882a593Smuzhiyun			pinctrl-single,register-width = <32>;
52*4882a593Smuzhiyun			pinctrl-single,function-mask = <0x1>;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun			pinmux_gpio_gpio: pinmux_gpio_gpio {
55*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x3>;
56*4882a593Smuzhiyun			};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun			pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
59*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x30>;
60*4882a593Smuzhiyun			};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun			pinmux_i2s_gpio: pinmux_i2s_gpio {
63*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x40 0xc0>;
64*4882a593Smuzhiyun			};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun			pinmux_uart0_uart: pinmux_uart0_uart0 {
67*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x300>;
68*4882a593Smuzhiyun			};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun			pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
71*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0xc00>;
72*4882a593Smuzhiyun			};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			pinmux_sdmode_gpio: pinmux_sdmode_gpio {
75*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x400 0xc00>;
76*4882a593Smuzhiyun			};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun			pinmux_spi_spi: pinmux_spi_spi {
79*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x1000>;
80*4882a593Smuzhiyun			};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			pinmux_refclk_gpio: pinmux_refclk_gpio {
83*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x40000 0x40000>;
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun			pinmux_i2c_i2c: pinmux_i2c_i2c {
87*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x300000>;
88*4882a593Smuzhiyun			};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun			pinmux_uart1_uart: pinmux_uart1_uart1 {
91*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x3000000>;
92*4882a593Smuzhiyun			};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun			pinmux_uart2_uart: pinmux_uart2_uart {
95*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0xc000000>;
96*4882a593Smuzhiyun			};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun			pinmux_pwm0_pwm: pinmux_pwm0_pwm {
99*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0x30000000>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			pinmux_pwm0_gpio: pinmux_pwm0_gpio {
103*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x10000000
104*4882a593Smuzhiyun						       0x30000000>;
105*4882a593Smuzhiyun			};
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun			pinmux_pwm1_pwm: pinmux_pwm1_pwm {
108*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x0 0xc0000000>;
109*4882a593Smuzhiyun			};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun			pinmux_pwm1_gpio: pinmux_pwm1_gpio {
112*4882a593Smuzhiyun				pinctrl-single,bits = <0x0 0x40000000
113*4882a593Smuzhiyun						       0xc0000000>;
114*4882a593Smuzhiyun			};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun			pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
117*4882a593Smuzhiyun				pinctrl-single,bits = <0x4 0x4 0xc>;
118*4882a593Smuzhiyun			};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun			pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
121*4882a593Smuzhiyun				pinctrl-single,bits = <0x4 0x10 0x30>;
122*4882a593Smuzhiyun			};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun			pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
125*4882a593Smuzhiyun				pinctrl-single,bits = <0x4 0x40 0xc0>;
126*4882a593Smuzhiyun			};
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun			pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
129*4882a593Smuzhiyun				pinctrl-single,bits = <0x4 0x100 0x300>;
130*4882a593Smuzhiyun			};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun			pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
133*4882a593Smuzhiyun				pinctrl-single,bits = <0x4 0x400 0xc00>;
134*4882a593Smuzhiyun			};
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		watchdog: watchdog@100 {
138*4882a593Smuzhiyun			compatible = "mediatek,mt7621-wdt";
139*4882a593Smuzhiyun			reg = <0x100 0x30>;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun			resets = <&resetc 8>;
142*4882a593Smuzhiyun			reset-names = "wdt";
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun			interrupt-parent = <&intc>;
145*4882a593Smuzhiyun			interrupts = <24>;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun			status = "disabled";
148*4882a593Smuzhiyun		};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		intc: interrupt-controller@200 {
151*4882a593Smuzhiyun			compatible = "ralink,rt2880-intc";
152*4882a593Smuzhiyun			reg = <0x200 0x100>;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun			interrupt-controller;
155*4882a593Smuzhiyun			#interrupt-cells = <1>;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun			resets = <&resetc 9>;
158*4882a593Smuzhiyun			reset-names = "intc";
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun			interrupt-parent = <&cpuintc>;
161*4882a593Smuzhiyun			interrupts = <2>;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun			ralink,intc-registers = <0x9c 0xa0
164*4882a593Smuzhiyun						 0x6c 0xa4
165*4882a593Smuzhiyun						 0x80 0x78>;
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		memory-controller@300 {
169*4882a593Smuzhiyun			compatible = "ralink,mt7620a-memc";
170*4882a593Smuzhiyun			reg = <0x300 0x100>;
171*4882a593Smuzhiyun		};
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun		gpio: gpio@600 {
174*4882a593Smuzhiyun			compatible = "mediatek,mt7621-gpio";
175*4882a593Smuzhiyun			reg = <0x600 0x100>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun			gpio-controller;
178*4882a593Smuzhiyun			interrupt-controller;
179*4882a593Smuzhiyun			#gpio-cells = <2>;
180*4882a593Smuzhiyun			#interrupt-cells = <2>;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun			interrupt-parent = <&intc>;
183*4882a593Smuzhiyun			interrupts = <6>;
184*4882a593Smuzhiyun		};
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		spi: spi@b00 {
187*4882a593Smuzhiyun			compatible = "ralink,mt7621-spi";
188*4882a593Smuzhiyun			reg = <0xb00 0x100>;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun			pinctrl-names = "default";
191*4882a593Smuzhiyun			pinctrl-0 = <&pinmux_spi_spi>;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun			resets = <&resetc 18>;
194*4882a593Smuzhiyun			reset-names = "spi";
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun			#address-cells = <1>;
197*4882a593Smuzhiyun			#size-cells = <0>;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun			status = "disabled";
200*4882a593Smuzhiyun		};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun		i2c: i2c@900 {
203*4882a593Smuzhiyun			compatible = "mediatek,mt7621-i2c";
204*4882a593Smuzhiyun			reg = <0x900 0x100>;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun			pinctrl-names = "default";
207*4882a593Smuzhiyun			pinctrl-0 = <&pinmux_i2c_i2c>;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun			resets = <&resetc 16>;
210*4882a593Smuzhiyun			reset-names = "i2c";
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun			#address-cells = <1>;
213*4882a593Smuzhiyun			#size-cells = <0>;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun			status = "disabled";
216*4882a593Smuzhiyun		};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun		uart0: uartlite@c00 {
219*4882a593Smuzhiyun			compatible = "ns16550a";
220*4882a593Smuzhiyun			reg = <0xc00 0x100>;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun			pinctrl-names = "default";
223*4882a593Smuzhiyun			pinctrl-0 = <&pinmux_uart0_uart>;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun			resets = <&resetc 12>;
226*4882a593Smuzhiyun			reset-names = "uart0";
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun			interrupt-parent = <&intc>;
229*4882a593Smuzhiyun			interrupts = <20>;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun			reg-shift = <2>;
232*4882a593Smuzhiyun		};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun		uart1: uart1@d00 {
235*4882a593Smuzhiyun			compatible = "ns16550a";
236*4882a593Smuzhiyun			reg = <0xd00 0x100>;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun			pinctrl-names = "default";
239*4882a593Smuzhiyun			pinctrl-0 = <&pinmux_uart1_uart>;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun			resets = <&resetc 19>;
242*4882a593Smuzhiyun			reset-names = "uart1";
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun			interrupt-parent = <&intc>;
245*4882a593Smuzhiyun			interrupts = <21>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun			reg-shift = <2>;
248*4882a593Smuzhiyun		};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun		uart2: uart2@e00 {
251*4882a593Smuzhiyun			compatible = "ns16550a";
252*4882a593Smuzhiyun			reg = <0xe00 0x100>;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun			pinctrl-names = "default";
255*4882a593Smuzhiyun			pinctrl-0 = <&pinmux_uart2_uart>;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun			resets = <&resetc 20>;
258*4882a593Smuzhiyun			reset-names = "uart2";
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun			interrupt-parent = <&intc>;
261*4882a593Smuzhiyun			interrupts = <22>;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun			reg-shift = <2>;
264*4882a593Smuzhiyun		};
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun	usb_phy: usb-phy@10120000 {
268*4882a593Smuzhiyun		compatible = "mediatek,mt7628-usbphy";
269*4882a593Smuzhiyun		reg = <0x10120000 0x1000>;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun		#phy-cells = <0>;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun		ralink,sysctl = <&sysc>;
274*4882a593Smuzhiyun		resets = <&resetc 22 &resetc 25>;
275*4882a593Smuzhiyun		reset-names = "host", "device";
276*4882a593Smuzhiyun	};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun	ehci@101c0000 {
279*4882a593Smuzhiyun		compatible = "generic-ehci";
280*4882a593Smuzhiyun		reg = <0x101c0000 0x1000>;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun		phys = <&usb_phy>;
283*4882a593Smuzhiyun		phy-names = "usb";
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun		interrupt-parent = <&intc>;
286*4882a593Smuzhiyun		interrupts = <18>;
287*4882a593Smuzhiyun	};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun	wmac: wmac@10300000 {
290*4882a593Smuzhiyun		compatible = "mediatek,mt7628-wmac";
291*4882a593Smuzhiyun		reg = <0x10300000 0x100000>;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun		interrupt-parent = <&cpuintc>;
294*4882a593Smuzhiyun		interrupts = <6>;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun		status = "disabled";
297*4882a593Smuzhiyun	};
298*4882a593Smuzhiyun};
299