1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun #address-cells = <1>; 4*4882a593Smuzhiyun #size-cells = <1>; 5*4882a593Smuzhiyun compatible = "ralink,mtk7620a-soc"; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun cpu@0 { 9*4882a593Smuzhiyun compatible = "mips,mips24KEc"; 10*4882a593Smuzhiyun }; 11*4882a593Smuzhiyun }; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpuintc: cpuintc { 14*4882a593Smuzhiyun #address-cells = <0>; 15*4882a593Smuzhiyun #interrupt-cells = <1>; 16*4882a593Smuzhiyun interrupt-controller; 17*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun palmbus@10000000 { 21*4882a593Smuzhiyun compatible = "palmbus"; 22*4882a593Smuzhiyun reg = <0x10000000 0x200000>; 23*4882a593Smuzhiyun ranges = <0x0 0x10000000 0x1FFFFF>; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <1>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun sysc@0 { 29*4882a593Smuzhiyun compatible = "ralink,mt7620a-sysc"; 30*4882a593Smuzhiyun reg = <0x0 0x100>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun intc: intc@200 { 34*4882a593Smuzhiyun compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc"; 35*4882a593Smuzhiyun reg = <0x200 0x100>; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun interrupt-controller; 38*4882a593Smuzhiyun #interrupt-cells = <1>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 41*4882a593Smuzhiyun interrupts = <2>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun memc@300 { 45*4882a593Smuzhiyun compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc"; 46*4882a593Smuzhiyun reg = <0x300 0x100>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun uartlite@c00 { 50*4882a593Smuzhiyun compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; 51*4882a593Smuzhiyun reg = <0xc00 0x100>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun interrupt-parent = <&intc>; 54*4882a593Smuzhiyun interrupts = <12>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun reg-shift = <2>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun}; 60