1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun#include <dt-bindings/clock/ath79-clk.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/ { 5*4882a593Smuzhiyun compatible = "qca,ar9132"; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #address-cells = <1>; 8*4882a593Smuzhiyun #size-cells = <1>; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun cpus { 11*4882a593Smuzhiyun #address-cells = <1>; 12*4882a593Smuzhiyun #size-cells = <0>; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun cpu@0 { 15*4882a593Smuzhiyun device_type = "cpu"; 16*4882a593Smuzhiyun compatible = "mips,mips24Kc"; 17*4882a593Smuzhiyun clocks = <&pll ATH79_CLK_CPU>; 18*4882a593Smuzhiyun reg = <0>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpuintc: interrupt-controller { 23*4882a593Smuzhiyun compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc"; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun interrupt-controller; 26*4882a593Smuzhiyun #interrupt-cells = <1>; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>; 29*4882a593Smuzhiyun qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>, 30*4882a593Smuzhiyun <&ddr_ctrl 0>, <&ddr_ctrl 1>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun ahb { 34*4882a593Smuzhiyun compatible = "simple-bus"; 35*4882a593Smuzhiyun ranges; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <1>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun apb { 43*4882a593Smuzhiyun compatible = "simple-bus"; 44*4882a593Smuzhiyun ranges; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <1>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun interrupt-parent = <&miscintc>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun ddr_ctrl: memory-controller@18000000 { 52*4882a593Smuzhiyun compatible = "qca,ar9132-ddr-controller", 53*4882a593Smuzhiyun "qca,ar7240-ddr-controller"; 54*4882a593Smuzhiyun reg = <0x18000000 0x100>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #qca,ddr-wb-channel-cells = <1>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun uart: uart@18020000 { 60*4882a593Smuzhiyun compatible = "ns8250"; 61*4882a593Smuzhiyun reg = <0x18020000 0x20>; 62*4882a593Smuzhiyun interrupts = <3>; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun clocks = <&pll ATH79_CLK_AHB>; 65*4882a593Smuzhiyun clock-names = "uart"; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun reg-io-width = <4>; 68*4882a593Smuzhiyun reg-shift = <2>; 69*4882a593Smuzhiyun no-loopback-test; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun status = "disabled"; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun gpio: gpio@18040000 { 75*4882a593Smuzhiyun compatible = "qca,ar9132-gpio", 76*4882a593Smuzhiyun "qca,ar7100-gpio"; 77*4882a593Smuzhiyun reg = <0x18040000 0x30>; 78*4882a593Smuzhiyun interrupts = <2>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun ngpios = <22>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun gpio-controller; 83*4882a593Smuzhiyun #gpio-cells = <2>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun interrupt-controller; 86*4882a593Smuzhiyun #interrupt-cells = <2>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun pll: pll-controller@18050000 { 90*4882a593Smuzhiyun compatible = "qca,ar9132-pll", 91*4882a593Smuzhiyun "qca,ar9130-pll"; 92*4882a593Smuzhiyun reg = <0x18050000 0x20>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun clock-names = "ref"; 95*4882a593Smuzhiyun /* The board must provides the ref clock */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #clock-cells = <1>; 98*4882a593Smuzhiyun clock-output-names = "cpu", "ddr", "ahb"; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun wdt: wdt@18060008 { 102*4882a593Smuzhiyun compatible = "qca,ar7130-wdt"; 103*4882a593Smuzhiyun reg = <0x18060008 0x8>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun interrupts = <4>; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun clocks = <&pll ATH79_CLK_AHB>; 108*4882a593Smuzhiyun clock-names = "wdt"; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun miscintc: interrupt-controller@18060010 { 112*4882a593Smuzhiyun compatible = "qca,ar9132-misc-intc", 113*4882a593Smuzhiyun "qca,ar7100-misc-intc"; 114*4882a593Smuzhiyun reg = <0x18060010 0x8>; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 117*4882a593Smuzhiyun interrupts = <6>; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun interrupt-controller; 120*4882a593Smuzhiyun #interrupt-cells = <1>; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun rst: reset-controller@1806001c { 124*4882a593Smuzhiyun compatible = "qca,ar9132-reset", 125*4882a593Smuzhiyun "qca,ar7100-reset"; 126*4882a593Smuzhiyun reg = <0x1806001c 0x4>; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #reset-cells = <1>; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun usb: usb@1b000100 { 133*4882a593Smuzhiyun compatible = "qca,ar7100-ehci", "generic-ehci"; 134*4882a593Smuzhiyun reg = <0x1b000100 0x100>; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun interrupts = <3>; 137*4882a593Smuzhiyun resets = <&rst 5>; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun has-transaction-translator; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun phy-names = "usb"; 142*4882a593Smuzhiyun phys = <&usb_phy>; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun status = "disabled"; 145*4882a593Smuzhiyun }; 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun spi: spi@1f000000 { 148*4882a593Smuzhiyun compatible = "qca,ar9132-spi", "qca,ar7100-spi"; 149*4882a593Smuzhiyun reg = <0x1f000000 0x10>; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun clocks = <&pll ATH79_CLK_AHB>; 152*4882a593Smuzhiyun clock-names = "ahb"; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun status = "disabled"; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #address-cells = <1>; 157*4882a593Smuzhiyun #size-cells = <0>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun usb_phy: usb-phy { 162*4882a593Smuzhiyun compatible = "qca,ar7100-usb-phy"; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun reset-names = "phy", "suspend-override"; 165*4882a593Smuzhiyun resets = <&rst 4>, <&rst 3>; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #phy-cells = <0>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun status = "disabled"; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun}; 172