1*4882a593Smuzhiyun/dts-v1/; 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun/ { 4*4882a593Smuzhiyun #address-cells = <1>; 5*4882a593Smuzhiyun #size-cells = <1>; 6*4882a593Smuzhiyun compatible = "ni,169445"; 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun cpus { 9*4882a593Smuzhiyun #address-cells = <1>; 10*4882a593Smuzhiyun #size-cells = <0>; 11*4882a593Smuzhiyun cpu@0 { 12*4882a593Smuzhiyun device_type = "cpu"; 13*4882a593Smuzhiyun compatible = "mti,mips14KEc"; 14*4882a593Smuzhiyun clocks = <&baseclk>; 15*4882a593Smuzhiyun reg = <0>; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun memory@0 { 20*4882a593Smuzhiyun device_type = "memory"; 21*4882a593Smuzhiyun reg = <0x0 0x10000000>; 22*4882a593Smuzhiyun }; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun baseclk: baseclock { 25*4882a593Smuzhiyun compatible = "fixed-clock"; 26*4882a593Smuzhiyun #clock-cells = <0>; 27*4882a593Smuzhiyun clock-frequency = <50000000>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpu_intc: interrupt-controller { 31*4882a593Smuzhiyun #address-cells = <0>; 32*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 33*4882a593Smuzhiyun interrupt-controller; 34*4882a593Smuzhiyun #interrupt-cells = <1>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun ahb@1f300000 { 38*4882a593Smuzhiyun compatible = "simple-bus"; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <1>; 41*4882a593Smuzhiyun ranges = <0x0 0x1f300000 0x80FFF>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun gpio1: gpio@10 { 44*4882a593Smuzhiyun compatible = "ni,169445-nand-gpio"; 45*4882a593Smuzhiyun reg = <0x10 0x4>; 46*4882a593Smuzhiyun reg-names = "dat"; 47*4882a593Smuzhiyun gpio-controller; 48*4882a593Smuzhiyun #gpio-cells = <2>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun gpio2: gpio@14 { 52*4882a593Smuzhiyun compatible = "ni,169445-nand-gpio"; 53*4882a593Smuzhiyun reg = <0x14 0x4>; 54*4882a593Smuzhiyun reg-names = "dat"; 55*4882a593Smuzhiyun gpio-controller; 56*4882a593Smuzhiyun #gpio-cells = <2>; 57*4882a593Smuzhiyun no-output; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun nand@0 { 61*4882a593Smuzhiyun compatible = "gpio-control-nand"; 62*4882a593Smuzhiyun nand-on-flash-bbt; 63*4882a593Smuzhiyun nand-ecc-mode = "soft_bch"; 64*4882a593Smuzhiyun nand-ecc-step-size = <512>; 65*4882a593Smuzhiyun nand-ecc-strength = <4>; 66*4882a593Smuzhiyun reg = <0x0 4>; 67*4882a593Smuzhiyun gpios = <&gpio2 0 0>, /* rdy */ 68*4882a593Smuzhiyun <&gpio1 1 0>, /* nce */ 69*4882a593Smuzhiyun <&gpio1 2 0>, /* ale */ 70*4882a593Smuzhiyun <&gpio1 3 0>, /* cle */ 71*4882a593Smuzhiyun <&gpio1 4 0>; /* nwp */ 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun serial@80000 { 75*4882a593Smuzhiyun compatible = "ns16550a"; 76*4882a593Smuzhiyun reg = <0x80000 0x1000>; 77*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 78*4882a593Smuzhiyun interrupts = <6>; 79*4882a593Smuzhiyun clocks = <&baseclk>; 80*4882a593Smuzhiyun reg-shift = <0>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun ethernet@40000 { 84*4882a593Smuzhiyun compatible = "snps,dwmac-4.10a"; 85*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 86*4882a593Smuzhiyun interrupts = <5>; 87*4882a593Smuzhiyun interrupt-names = "macirq"; 88*4882a593Smuzhiyun reg = <0x40000 0x2000>; 89*4882a593Smuzhiyun clock-names = "stmmaceth", "pclk"; 90*4882a593Smuzhiyun clocks = <&baseclk>, <&baseclk>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun phy-mode = "rgmii"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun fixed-link { 95*4882a593Smuzhiyun speed = <1000>; 96*4882a593Smuzhiyun full-duplex; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun}; 101