1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun/* Copyright (c) 2017 Microsemi Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/dts-v1/; 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun#include "ocelot.dtsi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/ { 9*4882a593Smuzhiyun compatible = "mscc,ocelot-pcb123", "mscc,ocelot"; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun chosen { 12*4882a593Smuzhiyun stdout-path = "serial0:115200n8"; 13*4882a593Smuzhiyun }; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun memory@0 { 16*4882a593Smuzhiyun device_type = "memory"; 17*4882a593Smuzhiyun reg = <0x0 0x0e000000>; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&uart0 { 22*4882a593Smuzhiyun status = "okay"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&uart2 { 26*4882a593Smuzhiyun status = "okay"; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&spi { 30*4882a593Smuzhiyun status = "okay"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun flash@0 { 33*4882a593Smuzhiyun compatible = "macronix,mx25l25635f", "jedec,spi-nor"; 34*4882a593Smuzhiyun spi-max-frequency = <20000000>; 35*4882a593Smuzhiyun reg = <0>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun&i2c { 40*4882a593Smuzhiyun clock-frequency = <100000>; 41*4882a593Smuzhiyun i2c-sda-hold-time-ns = <300>; 42*4882a593Smuzhiyun status = "okay"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&mdio0 { 46*4882a593Smuzhiyun status = "okay"; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun&port0 { 50*4882a593Smuzhiyun phy-handle = <&phy0>; 51*4882a593Smuzhiyun}; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun&port1 { 54*4882a593Smuzhiyun phy-handle = <&phy1>; 55*4882a593Smuzhiyun}; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&port2 { 58*4882a593Smuzhiyun phy-handle = <&phy2>; 59*4882a593Smuzhiyun}; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun&port3 { 62*4882a593Smuzhiyun phy-handle = <&phy3>; 63*4882a593Smuzhiyun}; 64