xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/mscc/ocelot_pcb120.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2*4882a593Smuzhiyun/* Copyright (c) 2017 Microsemi Corporation */
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun/dts-v1/;
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
7*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
8*4882a593Smuzhiyun#include <dt-bindings/phy/phy-ocelot-serdes.h>
9*4882a593Smuzhiyun#include "ocelot.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	chosen {
15*4882a593Smuzhiyun		stdout-path = "serial0:115200n8";
16*4882a593Smuzhiyun	};
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun	memory@0 {
19*4882a593Smuzhiyun		device_type = "memory";
20*4882a593Smuzhiyun		reg = <0x0 0x0e000000>;
21*4882a593Smuzhiyun	};
22*4882a593Smuzhiyun};
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun&gpio {
25*4882a593Smuzhiyun	phy_int_pins: phy_int_pins {
26*4882a593Smuzhiyun		pins = "GPIO_4";
27*4882a593Smuzhiyun		function = "gpio";
28*4882a593Smuzhiyun	};
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	phy_load_save_pins: phy_load_save_pins {
31*4882a593Smuzhiyun		pins = "GPIO_10";
32*4882a593Smuzhiyun		function = "ptp2";
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun&mdio0 {
37*4882a593Smuzhiyun	status = "okay";
38*4882a593Smuzhiyun};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun&mdio1 {
41*4882a593Smuzhiyun	status = "okay";
42*4882a593Smuzhiyun	pinctrl-names = "default";
43*4882a593Smuzhiyun	pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	phy7: ethernet-phy@0 {
46*4882a593Smuzhiyun		reg = <0>;
47*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
48*4882a593Smuzhiyun		interrupt-parent = <&gpio>;
49*4882a593Smuzhiyun		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
50*4882a593Smuzhiyun	};
51*4882a593Smuzhiyun	phy6: ethernet-phy@1 {
52*4882a593Smuzhiyun		reg = <1>;
53*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
54*4882a593Smuzhiyun		interrupt-parent = <&gpio>;
55*4882a593Smuzhiyun		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
56*4882a593Smuzhiyun	};
57*4882a593Smuzhiyun	phy5: ethernet-phy@2 {
58*4882a593Smuzhiyun		reg = <2>;
59*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
60*4882a593Smuzhiyun		interrupt-parent = <&gpio>;
61*4882a593Smuzhiyun		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
62*4882a593Smuzhiyun	};
63*4882a593Smuzhiyun	phy4: ethernet-phy@3 {
64*4882a593Smuzhiyun		reg = <3>;
65*4882a593Smuzhiyun		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
66*4882a593Smuzhiyun		interrupt-parent = <&gpio>;
67*4882a593Smuzhiyun		load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun};
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun&port0 {
72*4882a593Smuzhiyun	phy-handle = <&phy0>;
73*4882a593Smuzhiyun};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun&port1 {
76*4882a593Smuzhiyun	phy-handle = <&phy1>;
77*4882a593Smuzhiyun};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun&port2 {
80*4882a593Smuzhiyun	phy-handle = <&phy2>;
81*4882a593Smuzhiyun};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun&port3 {
84*4882a593Smuzhiyun	phy-handle = <&phy3>;
85*4882a593Smuzhiyun};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun&port4 {
88*4882a593Smuzhiyun	phy-handle = <&phy7>;
89*4882a593Smuzhiyun	phy-mode = "sgmii";
90*4882a593Smuzhiyun	phys = <&serdes 4 SERDES1G(2)>;
91*4882a593Smuzhiyun};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun&port5 {
94*4882a593Smuzhiyun	phy-handle = <&phy4>;
95*4882a593Smuzhiyun	phy-mode = "sgmii";
96*4882a593Smuzhiyun	phys = <&serdes 5 SERDES1G(5)>;
97*4882a593Smuzhiyun};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun&port6 {
100*4882a593Smuzhiyun	phy-handle = <&phy6>;
101*4882a593Smuzhiyun	phy-mode = "sgmii";
102*4882a593Smuzhiyun	phys = <&serdes 6 SERDES1G(3)>;
103*4882a593Smuzhiyun};
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun&port9 {
106*4882a593Smuzhiyun	phy-handle = <&phy5>;
107*4882a593Smuzhiyun	phy-mode = "sgmii";
108*4882a593Smuzhiyun	phys = <&serdes 9 SERDES1G(4)>;
109*4882a593Smuzhiyun};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun&uart0 {
112*4882a593Smuzhiyun	status = "okay";
113*4882a593Smuzhiyun};
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun&uart2 {
116*4882a593Smuzhiyun	status = "okay";
117*4882a593Smuzhiyun};
118