xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/ingenic/ci20.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/dts-v1/;
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun#include "jz4780.dtsi"
5*4882a593Smuzhiyun#include <dt-bindings/clock/ingenic,tcu.h>
6*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/irq.h>
9*4882a593Smuzhiyun#include <dt-bindings/regulator/active-semi,8865-regulator.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	compatible = "img,ci20", "ingenic,jz4780";
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	aliases {
15*4882a593Smuzhiyun		serial0 = &uart0;
16*4882a593Smuzhiyun		serial1 = &uart1;
17*4882a593Smuzhiyun		serial3 = &uart3;
18*4882a593Smuzhiyun		serial4 = &uart4;
19*4882a593Smuzhiyun	};
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	chosen {
22*4882a593Smuzhiyun		stdout-path = &uart4;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	memory {
26*4882a593Smuzhiyun		device_type = "memory";
27*4882a593Smuzhiyun		reg = <0x0 0x10000000
28*4882a593Smuzhiyun		       0x30000000 0x30000000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	gpio-keys {
32*4882a593Smuzhiyun		compatible = "gpio-keys";
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun		sw1 {
35*4882a593Smuzhiyun			label = "ci20:sw1";
36*4882a593Smuzhiyun			linux,code = <KEY_F13>;
37*4882a593Smuzhiyun			gpios = <&gpd 17 GPIO_ACTIVE_HIGH>;
38*4882a593Smuzhiyun			wakeup-source;
39*4882a593Smuzhiyun		};
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	leds {
43*4882a593Smuzhiyun		compatible = "gpio-leds";
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		led0 {
46*4882a593Smuzhiyun			label = "ci20:red:led0";
47*4882a593Smuzhiyun			gpios = <&gpc 3 GPIO_ACTIVE_HIGH>;
48*4882a593Smuzhiyun			linux,default-trigger = "none";
49*4882a593Smuzhiyun		};
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		led1 {
52*4882a593Smuzhiyun			label = "ci20:red:led1";
53*4882a593Smuzhiyun			gpios = <&gpc 2 GPIO_ACTIVE_HIGH>;
54*4882a593Smuzhiyun			linux,default-trigger = "nand-disk";
55*4882a593Smuzhiyun		};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun		led2 {
58*4882a593Smuzhiyun			label = "ci20:red:led2";
59*4882a593Smuzhiyun			gpios = <&gpc 1 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun			linux,default-trigger = "cpu1";
61*4882a593Smuzhiyun		};
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		led3 {
64*4882a593Smuzhiyun			label = "ci20:red:led3";
65*4882a593Smuzhiyun			gpios = <&gpc 0 GPIO_ACTIVE_HIGH>;
66*4882a593Smuzhiyun			linux,default-trigger = "cpu0";
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun	};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	eth0_power: fixedregulator@0 {
71*4882a593Smuzhiyun		compatible = "regulator-fixed";
72*4882a593Smuzhiyun		regulator-name = "eth0_power";
73*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
74*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
75*4882a593Smuzhiyun		gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
76*4882a593Smuzhiyun		enable-active-high;
77*4882a593Smuzhiyun	};
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun	ir: ir {
80*4882a593Smuzhiyun		compatible = "gpio-ir-receiver";
81*4882a593Smuzhiyun		gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun	wlan0_power: fixedregulator@1 {
85*4882a593Smuzhiyun		compatible = "regulator-fixed";
86*4882a593Smuzhiyun		regulator-name = "wlan0_power";
87*4882a593Smuzhiyun		gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
88*4882a593Smuzhiyun		enable-active-high;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun};
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun&ext {
93*4882a593Smuzhiyun	clock-frequency = <48000000>;
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun&mmc0 {
97*4882a593Smuzhiyun	status = "okay";
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun	bus-width = <4>;
100*4882a593Smuzhiyun	max-frequency = <50000000>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	pinctrl-names = "default";
103*4882a593Smuzhiyun	pinctrl-0 = <&pins_mmc0>;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun	cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
106*4882a593Smuzhiyun};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun&mmc1 {
109*4882a593Smuzhiyun	status = "okay";
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	bus-width = <4>;
112*4882a593Smuzhiyun	max-frequency = <50000000>;
113*4882a593Smuzhiyun	non-removable;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun	pinctrl-names = "default";
116*4882a593Smuzhiyun	pinctrl-0 = <&pins_mmc1>;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	brcmf: wifi@1 {
119*4882a593Smuzhiyun/*		reg = <4>;*/
120*4882a593Smuzhiyun		compatible = "brcm,bcm4330-fmac";
121*4882a593Smuzhiyun		vcc-supply = <&wlan0_power>;
122*4882a593Smuzhiyun		device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
123*4882a593Smuzhiyun		shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
124*4882a593Smuzhiyun	};
125*4882a593Smuzhiyun};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun&uart0 {
128*4882a593Smuzhiyun	status = "okay";
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun	pinctrl-names = "default";
131*4882a593Smuzhiyun	pinctrl-0 = <&pins_uart0>;
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&uart1 {
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun	pinctrl-names = "default";
138*4882a593Smuzhiyun	pinctrl-0 = <&pins_uart1>;
139*4882a593Smuzhiyun};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun&uart2 {
142*4882a593Smuzhiyun	status = "okay";
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun	pinctrl-names = "default";
145*4882a593Smuzhiyun	pinctrl-0 = <&pins_uart2>;
146*4882a593Smuzhiyun	uart-has-rtscts;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun	bluetooth {
149*4882a593Smuzhiyun		compatible = "brcm,bcm4330-bt";
150*4882a593Smuzhiyun		reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
151*4882a593Smuzhiyun		vcc-supply = <&wlan0_power>;
152*4882a593Smuzhiyun		device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
153*4882a593Smuzhiyun		host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
154*4882a593Smuzhiyun		shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
155*4882a593Smuzhiyun	};
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&uart3 {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun	pinctrl-names = "default";
162*4882a593Smuzhiyun	pinctrl-0 = <&pins_uart3>;
163*4882a593Smuzhiyun};
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun&uart4 {
166*4882a593Smuzhiyun	status = "okay";
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun	pinctrl-names = "default";
169*4882a593Smuzhiyun	pinctrl-0 = <&pins_uart4>;
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&i2c0 {
173*4882a593Smuzhiyun	status = "okay";
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun	pinctrl-names = "default";
176*4882a593Smuzhiyun	pinctrl-0 = <&pins_i2c0>;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	clock-frequency = <400000>;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun	act8600: act8600@5a {
181*4882a593Smuzhiyun		compatible = "active-semi,act8600";
182*4882a593Smuzhiyun		reg = <0x5a>;
183*4882a593Smuzhiyun		status = "okay";
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun		regulators {
186*4882a593Smuzhiyun			vddcore: SUDCDC1 {
187*4882a593Smuzhiyun				regulator-name = "DCDC_REG1";
188*4882a593Smuzhiyun				regulator-min-microvolt = <1100000>;
189*4882a593Smuzhiyun				regulator-max-microvolt = <1100000>;
190*4882a593Smuzhiyun				regulator-always-on;
191*4882a593Smuzhiyun			};
192*4882a593Smuzhiyun			vddmem: SUDCDC2 {
193*4882a593Smuzhiyun				regulator-name = "DCDC_REG2";
194*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
195*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
196*4882a593Smuzhiyun				regulator-always-on;
197*4882a593Smuzhiyun			};
198*4882a593Smuzhiyun			vcc_33: SUDCDC3 {
199*4882a593Smuzhiyun				regulator-name = "DCDC_REG3";
200*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
201*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
202*4882a593Smuzhiyun				regulator-always-on;
203*4882a593Smuzhiyun			};
204*4882a593Smuzhiyun			vcc_50: SUDCDC4 {
205*4882a593Smuzhiyun				regulator-name = "SUDCDC_REG4";
206*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
207*4882a593Smuzhiyun				regulator-max-microvolt = <5000000>;
208*4882a593Smuzhiyun				regulator-always-on;
209*4882a593Smuzhiyun			};
210*4882a593Smuzhiyun			vcc_25: LDO_REG5 {
211*4882a593Smuzhiyun				regulator-name = "LDO_REG5";
212*4882a593Smuzhiyun				regulator-min-microvolt = <2500000>;
213*4882a593Smuzhiyun				regulator-max-microvolt = <2500000>;
214*4882a593Smuzhiyun				regulator-always-on;
215*4882a593Smuzhiyun			};
216*4882a593Smuzhiyun			wifi_io: LDO_REG6 {
217*4882a593Smuzhiyun				regulator-name = "LDO_REG6";
218*4882a593Smuzhiyun				regulator-min-microvolt = <2500000>;
219*4882a593Smuzhiyun				regulator-max-microvolt = <2500000>;
220*4882a593Smuzhiyun				regulator-always-on;
221*4882a593Smuzhiyun			};
222*4882a593Smuzhiyun			vcc_28: LDO_REG7 {
223*4882a593Smuzhiyun				regulator-name = "LDO_REG7";
224*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
225*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
226*4882a593Smuzhiyun				regulator-always-on;
227*4882a593Smuzhiyun			};
228*4882a593Smuzhiyun			vcc_15: LDO_REG8 {
229*4882a593Smuzhiyun				regulator-name = "LDO_REG8";
230*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
231*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
232*4882a593Smuzhiyun				regulator-always-on;
233*4882a593Smuzhiyun			};
234*4882a593Smuzhiyun			vrtc_18: LDO_REG9 {
235*4882a593Smuzhiyun				regulator-name = "LDO_REG9";
236*4882a593Smuzhiyun				/* Despite the datasheet stating 3.3V
237*4882a593Smuzhiyun				 * for REG9 and the driver expecting that,
238*4882a593Smuzhiyun				 * REG9 outputs 1.8V.
239*4882a593Smuzhiyun				 * Likely the CI20 uses a proprietary
240*4882a593Smuzhiyun				 * factory programmed chip variant.
241*4882a593Smuzhiyun				 * Since this is a simple on/off LDO the
242*4882a593Smuzhiyun				 * exact values do not matter.
243*4882a593Smuzhiyun				 */
244*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
245*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
246*4882a593Smuzhiyun				regulator-always-on;
247*4882a593Smuzhiyun			};
248*4882a593Smuzhiyun			vcc_11: LDO_REG10 {
249*4882a593Smuzhiyun				regulator-name = "LDO_REG10";
250*4882a593Smuzhiyun				regulator-min-microvolt = <1200000>;
251*4882a593Smuzhiyun				regulator-max-microvolt = <1200000>;
252*4882a593Smuzhiyun				regulator-always-on;
253*4882a593Smuzhiyun			};
254*4882a593Smuzhiyun		};
255*4882a593Smuzhiyun	};
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&i2c1 {
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun	pinctrl-names = "default";
262*4882a593Smuzhiyun	pinctrl-0 = <&pins_i2c1>;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&i2c2 {
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun	pinctrl-names = "default";
270*4882a593Smuzhiyun	pinctrl-0 = <&pins_i2c2>;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun&i2c3 {
275*4882a593Smuzhiyun	status = "okay";
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun	pinctrl-names = "default";
278*4882a593Smuzhiyun	pinctrl-0 = <&pins_i2c3>;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&i2c4 {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun	pinctrl-names = "default";
286*4882a593Smuzhiyun	pinctrl-0 = <&pins_i2c4>;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	clock-frequency = <400000>;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun		rtc@51 {
291*4882a593Smuzhiyun			compatible = "nxp,pcf8563";
292*4882a593Smuzhiyun			reg = <0x51>;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun			interrupt-parent = <&gpf>;
295*4882a593Smuzhiyun			interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
296*4882a593Smuzhiyun		};
297*4882a593Smuzhiyun};
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun&nemc {
300*4882a593Smuzhiyun	status = "okay";
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun	nandc: nand-controller@1 {
303*4882a593Smuzhiyun		compatible = "ingenic,jz4780-nand";
304*4882a593Smuzhiyun		reg = <1 0 0x1000000>;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun		#address-cells = <1>;
307*4882a593Smuzhiyun		#size-cells = <0>;
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun		ingenic,bch-controller = <&bch>;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun		ingenic,nemc-tAS = <10>;
312*4882a593Smuzhiyun		ingenic,nemc-tAH = <5>;
313*4882a593Smuzhiyun		ingenic,nemc-tBP = <10>;
314*4882a593Smuzhiyun		ingenic,nemc-tAW = <15>;
315*4882a593Smuzhiyun		ingenic,nemc-tSTRV = <100>;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun		/*
318*4882a593Smuzhiyun		 * Only CLE/ALE are needed for the devices that are connected, rather
319*4882a593Smuzhiyun		 * than the full address line set.
320*4882a593Smuzhiyun		 */
321*4882a593Smuzhiyun		pinctrl-names = "default";
322*4882a593Smuzhiyun		pinctrl-0 = <&pins_nemc>;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun		nand@1 {
325*4882a593Smuzhiyun			reg = <1>;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun			nand-ecc-step-size = <1024>;
328*4882a593Smuzhiyun			nand-ecc-strength = <24>;
329*4882a593Smuzhiyun			nand-ecc-mode = "hw";
330*4882a593Smuzhiyun			nand-on-flash-bbt;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun			pinctrl-names = "default";
333*4882a593Smuzhiyun			pinctrl-0 = <&pins_nemc_cs1>;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun			partitions {
336*4882a593Smuzhiyun				compatible = "fixed-partitions";
337*4882a593Smuzhiyun				#address-cells = <2>;
338*4882a593Smuzhiyun				#size-cells = <2>;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun				partition@0 {
341*4882a593Smuzhiyun					label = "u-boot-spl";
342*4882a593Smuzhiyun					reg = <0x0 0x0 0x0 0x800000>;
343*4882a593Smuzhiyun				};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun				partition@800000 {
346*4882a593Smuzhiyun					label = "u-boot";
347*4882a593Smuzhiyun					reg = <0x0 0x800000 0x0 0x200000>;
348*4882a593Smuzhiyun				};
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun				partition@a00000 {
351*4882a593Smuzhiyun					label = "u-boot-env";
352*4882a593Smuzhiyun					reg = <0x0 0xa00000 0x0 0x200000>;
353*4882a593Smuzhiyun				};
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun				partition@c00000 {
356*4882a593Smuzhiyun					label = "boot";
357*4882a593Smuzhiyun					reg = <0x0 0xc00000 0x0 0x4000000>;
358*4882a593Smuzhiyun				};
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun				partition@4c00000 {
361*4882a593Smuzhiyun					label = "system";
362*4882a593Smuzhiyun					reg = <0x0 0x4c00000 0x1 0xfb400000>;
363*4882a593Smuzhiyun				};
364*4882a593Smuzhiyun			};
365*4882a593Smuzhiyun		};
366*4882a593Smuzhiyun	};
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun	dm9000@6 {
369*4882a593Smuzhiyun		compatible = "davicom,dm9000";
370*4882a593Smuzhiyun		davicom,no-eeprom;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun		pinctrl-names = "default";
373*4882a593Smuzhiyun		pinctrl-0 = <&pins_nemc_cs6>;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun		reg = <6 0 1   /* addr */
376*4882a593Smuzhiyun		       6 2 1>; /* data */
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun		ingenic,nemc-tAS = <15>;
379*4882a593Smuzhiyun		ingenic,nemc-tAH = <10>;
380*4882a593Smuzhiyun		ingenic,nemc-tBP = <20>;
381*4882a593Smuzhiyun		ingenic,nemc-tAW = <50>;
382*4882a593Smuzhiyun		ingenic,nemc-tSTRV = <100>;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun		reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
385*4882a593Smuzhiyun		vcc-supply = <&eth0_power>;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun		interrupt-parent = <&gpe>;
388*4882a593Smuzhiyun		interrupts = <19 4>;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun		nvmem-cells = <&eth0_addr>;
391*4882a593Smuzhiyun		nvmem-cell-names = "mac-address";
392*4882a593Smuzhiyun	};
393*4882a593Smuzhiyun};
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun&bch {
396*4882a593Smuzhiyun	status = "okay";
397*4882a593Smuzhiyun};
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun&pinctrl {
400*4882a593Smuzhiyun	pins_uart0: uart0 {
401*4882a593Smuzhiyun		function = "uart0";
402*4882a593Smuzhiyun		groups = "uart0-data";
403*4882a593Smuzhiyun		bias-disable;
404*4882a593Smuzhiyun	};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun	pins_uart1: uart1 {
407*4882a593Smuzhiyun		function = "uart1";
408*4882a593Smuzhiyun		groups = "uart1-data";
409*4882a593Smuzhiyun		bias-disable;
410*4882a593Smuzhiyun	};
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun	pins_uart2: uart2 {
413*4882a593Smuzhiyun		function = "uart2";
414*4882a593Smuzhiyun		groups = "uart2-data", "uart2-hwflow";
415*4882a593Smuzhiyun		bias-disable;
416*4882a593Smuzhiyun	};
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun	pins_uart3: uart3 {
419*4882a593Smuzhiyun		function = "uart3";
420*4882a593Smuzhiyun		groups = "uart3-data", "uart3-hwflow";
421*4882a593Smuzhiyun		bias-disable;
422*4882a593Smuzhiyun	};
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun	pins_uart4: uart4 {
425*4882a593Smuzhiyun		function = "uart4";
426*4882a593Smuzhiyun		groups = "uart4-data";
427*4882a593Smuzhiyun		bias-disable;
428*4882a593Smuzhiyun	};
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun	pins_i2c0: i2c0 {
431*4882a593Smuzhiyun		function = "i2c0";
432*4882a593Smuzhiyun		groups = "i2c0-data";
433*4882a593Smuzhiyun		bias-disable;
434*4882a593Smuzhiyun	};
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun	pins_i2c1: i2c1 {
437*4882a593Smuzhiyun		function = "i2c1";
438*4882a593Smuzhiyun		groups = "i2c1-data";
439*4882a593Smuzhiyun		bias-disable;
440*4882a593Smuzhiyun	};
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun	pins_i2c2: i2c2 {
443*4882a593Smuzhiyun		function = "i2c2";
444*4882a593Smuzhiyun		groups = "i2c2-data";
445*4882a593Smuzhiyun		bias-disable;
446*4882a593Smuzhiyun	};
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun	pins_i2c3: i2c3 {
449*4882a593Smuzhiyun		function = "i2c3";
450*4882a593Smuzhiyun		groups = "i2c3-data";
451*4882a593Smuzhiyun		bias-disable;
452*4882a593Smuzhiyun	};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun	pins_i2c4: i2c4 {
455*4882a593Smuzhiyun		function = "i2c4";
456*4882a593Smuzhiyun		groups = "i2c4-data-e";
457*4882a593Smuzhiyun		bias-disable;
458*4882a593Smuzhiyun	};
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun	pins_nemc: nemc {
461*4882a593Smuzhiyun		function = "nemc";
462*4882a593Smuzhiyun		groups = "nemc-data", "nemc-cle-ale", "nemc-rd-we", "nemc-frd-fwe";
463*4882a593Smuzhiyun		bias-disable;
464*4882a593Smuzhiyun	};
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun	pins_nemc_cs1: nemc-cs1 {
467*4882a593Smuzhiyun		function = "nemc-cs1";
468*4882a593Smuzhiyun		groups = "nemc-cs1";
469*4882a593Smuzhiyun		bias-disable;
470*4882a593Smuzhiyun	};
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun	pins_nemc_cs6: nemc-cs6 {
473*4882a593Smuzhiyun		function = "nemc-cs6";
474*4882a593Smuzhiyun		groups = "nemc-cs6";
475*4882a593Smuzhiyun		bias-disable;
476*4882a593Smuzhiyun	};
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun	pins_mmc0: mmc0 {
479*4882a593Smuzhiyun		function = "mmc0";
480*4882a593Smuzhiyun		groups = "mmc0-1bit-e", "mmc0-4bit-e";
481*4882a593Smuzhiyun		bias-disable;
482*4882a593Smuzhiyun	};
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun	pins_mmc1: mmc1 {
485*4882a593Smuzhiyun		function = "mmc1";
486*4882a593Smuzhiyun		groups = "mmc1-1bit-d", "mmc1-4bit-d";
487*4882a593Smuzhiyun		bias-disable;
488*4882a593Smuzhiyun	};
489*4882a593Smuzhiyun};
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun&tcu {
492*4882a593Smuzhiyun	/* 3 MHz for the system timer and clocksource */
493*4882a593Smuzhiyun	assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>;
494*4882a593Smuzhiyun	assigned-clock-rates = <3000000>, <3000000>;
495*4882a593Smuzhiyun};
496