1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun #address-cells = <1>; 4*4882a593Smuzhiyun #size-cells = <1>; 5*4882a593Smuzhiyun compatible = "brcm,bcm7346"; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <0>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun mips-hpt-frequency = <163125000>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpu@0 { 14*4882a593Smuzhiyun compatible = "brcm,bmips5000"; 15*4882a593Smuzhiyun device_type = "cpu"; 16*4882a593Smuzhiyun reg = <0>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpu@1 { 20*4882a593Smuzhiyun compatible = "brcm,bmips5000"; 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun reg = <1>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun aliases { 27*4882a593Smuzhiyun uart0 = &uart0; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun cpu_intc: interrupt-controller { 31*4882a593Smuzhiyun #address-cells = <0>; 32*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun interrupt-controller; 35*4882a593Smuzhiyun #interrupt-cells = <1>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clocks { 39*4882a593Smuzhiyun uart_clk: uart_clk { 40*4882a593Smuzhiyun compatible = "fixed-clock"; 41*4882a593Smuzhiyun #clock-cells = <0>; 42*4882a593Smuzhiyun clock-frequency = <81000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun upg_clk: upg_clk { 46*4882a593Smuzhiyun compatible = "fixed-clock"; 47*4882a593Smuzhiyun #clock-cells = <0>; 48*4882a593Smuzhiyun clock-frequency = <27000000>; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun rdb { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun compatible = "simple-bus"; 57*4882a593Smuzhiyun ranges = <0 0x10000000 0x01000000>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun periph_intc: interrupt-controller@411400 { 60*4882a593Smuzhiyun compatible = "brcm,bcm7038-l1-intc"; 61*4882a593Smuzhiyun reg = <0x411400 0x30>, <0x411600 0x30>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun #interrupt-cells = <1>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 67*4882a593Smuzhiyun interrupts = <2>, <3>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun sun_l2_intc: interrupt-controller@403000 { 71*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 72*4882a593Smuzhiyun reg = <0x403000 0x30>; 73*4882a593Smuzhiyun interrupt-controller; 74*4882a593Smuzhiyun #interrupt-cells = <1>; 75*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 76*4882a593Smuzhiyun interrupts = <51>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun gisb-arb@400000 { 80*4882a593Smuzhiyun compatible = "brcm,bcm7400-gisb-arb"; 81*4882a593Smuzhiyun reg = <0x400000 0xdc>; 82*4882a593Smuzhiyun native-endian; 83*4882a593Smuzhiyun interrupt-parent = <&sun_l2_intc>; 84*4882a593Smuzhiyun interrupts = <0>, <2>; 85*4882a593Smuzhiyun brcm,gisb-arb-master-mask = <0x673>; 86*4882a593Smuzhiyun brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0", 87*4882a593Smuzhiyun "rdc_0", "raaga_0", 88*4882a593Smuzhiyun "jtag_0", "svd_0"; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun upg_irq0_intc: interrupt-controller@406780 { 92*4882a593Smuzhiyun compatible = "brcm,bcm7120-l2-intc"; 93*4882a593Smuzhiyun reg = <0x406780 0x8>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun brcm,int-map-mask = <0x44>, <0xf000000>; 96*4882a593Smuzhiyun brcm,int-fwd-mask = <0x70000>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun interrupt-controller; 99*4882a593Smuzhiyun #interrupt-cells = <1>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 102*4882a593Smuzhiyun interrupts = <59>, <57>; 103*4882a593Smuzhiyun interrupt-names = "upg_main", "upg_bsc"; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun upg_aon_irq0_intc: interrupt-controller@408b80 { 107*4882a593Smuzhiyun compatible = "brcm,bcm7120-l2-intc"; 108*4882a593Smuzhiyun reg = <0x408b80 0x8>; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>; 111*4882a593Smuzhiyun brcm,int-fwd-mask = <0>; 112*4882a593Smuzhiyun brcm,irq-can-wake; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun interrupt-controller; 115*4882a593Smuzhiyun #interrupt-cells = <1>; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 118*4882a593Smuzhiyun interrupts = <60>, <58>, <62>; 119*4882a593Smuzhiyun interrupt-names = "upg_main_aon", "upg_bsc_aon", 120*4882a593Smuzhiyun "upg_spi"; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun sun_top_ctrl: syscon@404000 { 124*4882a593Smuzhiyun compatible = "brcm,bcm7346-sun-top-ctrl", "syscon"; 125*4882a593Smuzhiyun reg = <0x404000 0x51c>; 126*4882a593Smuzhiyun native-endian; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun reboot { 130*4882a593Smuzhiyun compatible = "brcm,brcmstb-reboot"; 131*4882a593Smuzhiyun syscon = <&sun_top_ctrl 0x304 0x308>; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun uart0: serial@406900 { 135*4882a593Smuzhiyun compatible = "ns16550a"; 136*4882a593Smuzhiyun reg = <0x406900 0x20>; 137*4882a593Smuzhiyun reg-io-width = <0x4>; 138*4882a593Smuzhiyun reg-shift = <0x2>; 139*4882a593Smuzhiyun native-endian; 140*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 141*4882a593Smuzhiyun interrupts = <64>; 142*4882a593Smuzhiyun clocks = <&uart_clk>; 143*4882a593Smuzhiyun status = "disabled"; 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun uart1: serial@406940 { 147*4882a593Smuzhiyun compatible = "ns16550a"; 148*4882a593Smuzhiyun reg = <0x406940 0x20>; 149*4882a593Smuzhiyun reg-io-width = <0x4>; 150*4882a593Smuzhiyun reg-shift = <0x2>; 151*4882a593Smuzhiyun native-endian; 152*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 153*4882a593Smuzhiyun interrupts = <65>; 154*4882a593Smuzhiyun clocks = <&uart_clk>; 155*4882a593Smuzhiyun status = "disabled"; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun uart2: serial@406980 { 159*4882a593Smuzhiyun compatible = "ns16550a"; 160*4882a593Smuzhiyun reg = <0x406980 0x20>; 161*4882a593Smuzhiyun reg-io-width = <0x4>; 162*4882a593Smuzhiyun reg-shift = <0x2>; 163*4882a593Smuzhiyun native-endian; 164*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 165*4882a593Smuzhiyun interrupts = <66>; 166*4882a593Smuzhiyun clocks = <&uart_clk>; 167*4882a593Smuzhiyun status = "disabled"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun bsca: i2c@406200 { 171*4882a593Smuzhiyun clock-frequency = <390000>; 172*4882a593Smuzhiyun compatible = "brcm,brcmstb-i2c"; 173*4882a593Smuzhiyun interrupt-parent = <&upg_irq0_intc>; 174*4882a593Smuzhiyun reg = <0x406200 0x58>; 175*4882a593Smuzhiyun interrupts = <24>; 176*4882a593Smuzhiyun interrupt-names = "upg_bsca"; 177*4882a593Smuzhiyun status = "disabled"; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun bscb: i2c@406280 { 181*4882a593Smuzhiyun clock-frequency = <390000>; 182*4882a593Smuzhiyun compatible = "brcm,brcmstb-i2c"; 183*4882a593Smuzhiyun interrupt-parent = <&upg_irq0_intc>; 184*4882a593Smuzhiyun reg = <0x406280 0x58>; 185*4882a593Smuzhiyun interrupts = <25>; 186*4882a593Smuzhiyun interrupt-names = "upg_bscb"; 187*4882a593Smuzhiyun status = "disabled"; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun bscc: i2c@406300 { 191*4882a593Smuzhiyun clock-frequency = <390000>; 192*4882a593Smuzhiyun compatible = "brcm,brcmstb-i2c"; 193*4882a593Smuzhiyun interrupt-parent = <&upg_irq0_intc>; 194*4882a593Smuzhiyun reg = <0x406300 0x58>; 195*4882a593Smuzhiyun interrupts = <26>; 196*4882a593Smuzhiyun interrupt-names = "upg_bscc"; 197*4882a593Smuzhiyun status = "disabled"; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun bscd: i2c@406380 { 201*4882a593Smuzhiyun clock-frequency = <390000>; 202*4882a593Smuzhiyun compatible = "brcm,brcmstb-i2c"; 203*4882a593Smuzhiyun interrupt-parent = <&upg_irq0_intc>; 204*4882a593Smuzhiyun reg = <0x406380 0x58>; 205*4882a593Smuzhiyun interrupts = <27>; 206*4882a593Smuzhiyun interrupt-names = "upg_bscd"; 207*4882a593Smuzhiyun status = "disabled"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun bsce: i2c@408980 { 211*4882a593Smuzhiyun clock-frequency = <390000>; 212*4882a593Smuzhiyun compatible = "brcm,brcmstb-i2c"; 213*4882a593Smuzhiyun interrupt-parent = <&upg_aon_irq0_intc>; 214*4882a593Smuzhiyun reg = <0x408980 0x58>; 215*4882a593Smuzhiyun interrupts = <27>; 216*4882a593Smuzhiyun interrupt-names = "upg_bsce"; 217*4882a593Smuzhiyun status = "disabled"; 218*4882a593Smuzhiyun }; 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun pwma: pwm@406580 { 221*4882a593Smuzhiyun compatible = "brcm,bcm7038-pwm"; 222*4882a593Smuzhiyun reg = <0x406580 0x28>; 223*4882a593Smuzhiyun #pwm-cells = <2>; 224*4882a593Smuzhiyun clocks = <&upg_clk>; 225*4882a593Smuzhiyun status = "disabled"; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun pwmb: pwm@406800 { 229*4882a593Smuzhiyun compatible = "brcm,bcm7038-pwm"; 230*4882a593Smuzhiyun reg = <0x406800 0x28>; 231*4882a593Smuzhiyun #pwm-cells = <2>; 232*4882a593Smuzhiyun clocks = <&upg_clk>; 233*4882a593Smuzhiyun status = "disabled"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun watchdog: watchdog@4067e8 { 237*4882a593Smuzhiyun clocks = <&upg_clk>; 238*4882a593Smuzhiyun compatible = "brcm,bcm7038-wdt"; 239*4882a593Smuzhiyun reg = <0x4067e8 0x14>; 240*4882a593Smuzhiyun status = "disabled"; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun aon_pm_l2_intc: interrupt-controller@408440 { 244*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 245*4882a593Smuzhiyun reg = <0x408440 0x30>; 246*4882a593Smuzhiyun interrupt-controller; 247*4882a593Smuzhiyun #interrupt-cells = <1>; 248*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 249*4882a593Smuzhiyun interrupts = <53>; 250*4882a593Smuzhiyun brcm,irq-can-wake; 251*4882a593Smuzhiyun }; 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun aon_ctrl: syscon@408000 { 254*4882a593Smuzhiyun compatible = "brcm,brcmstb-aon-ctrl"; 255*4882a593Smuzhiyun reg = <0x408000 0x100>, <0x408200 0x200>; 256*4882a593Smuzhiyun reg-names = "aon-ctrl", "aon-sram"; 257*4882a593Smuzhiyun }; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun timers: timer@4067c0 { 260*4882a593Smuzhiyun compatible = "brcm,brcmstb-timers"; 261*4882a593Smuzhiyun reg = <0x4067c0 0x40>; 262*4882a593Smuzhiyun }; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun upg_gio: gpio@406700 { 265*4882a593Smuzhiyun compatible = "brcm,brcmstb-gpio"; 266*4882a593Smuzhiyun reg = <0x406700 0x60>; 267*4882a593Smuzhiyun #gpio-cells = <2>; 268*4882a593Smuzhiyun #interrupt-cells = <2>; 269*4882a593Smuzhiyun gpio-controller; 270*4882a593Smuzhiyun interrupt-controller; 271*4882a593Smuzhiyun interrupt-parent = <&upg_irq0_intc>; 272*4882a593Smuzhiyun interrupts = <6>; 273*4882a593Smuzhiyun brcm,gpio-bank-widths = <32 32 16>; 274*4882a593Smuzhiyun }; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun upg_gio_aon: gpio@408c00 { 277*4882a593Smuzhiyun compatible = "brcm,brcmstb-gpio"; 278*4882a593Smuzhiyun reg = <0x408c00 0x60>; 279*4882a593Smuzhiyun #gpio-cells = <2>; 280*4882a593Smuzhiyun #interrupt-cells = <2>; 281*4882a593Smuzhiyun gpio-controller; 282*4882a593Smuzhiyun interrupt-controller; 283*4882a593Smuzhiyun interrupt-parent = <&upg_aon_irq0_intc>; 284*4882a593Smuzhiyun interrupts = <6>; 285*4882a593Smuzhiyun interrupts-extended = <&upg_aon_irq0_intc 6>, 286*4882a593Smuzhiyun <&aon_pm_l2_intc 5>; 287*4882a593Smuzhiyun wakeup-source; 288*4882a593Smuzhiyun brcm,gpio-bank-widths = <27 32 2>; 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun enet0: ethernet@430000 { 292*4882a593Smuzhiyun phy-mode = "internal"; 293*4882a593Smuzhiyun phy-handle = <&phy1>; 294*4882a593Smuzhiyun mac-address = [ 00 10 18 36 23 1a ]; 295*4882a593Smuzhiyun compatible = "brcm,genet-v2"; 296*4882a593Smuzhiyun #address-cells = <0x1>; 297*4882a593Smuzhiyun #size-cells = <0x1>; 298*4882a593Smuzhiyun reg = <0x430000 0x4c8c>; 299*4882a593Smuzhiyun interrupts = <24>, <25>; 300*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 301*4882a593Smuzhiyun status = "disabled"; 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun mdio@e14 { 304*4882a593Smuzhiyun compatible = "brcm,genet-mdio-v2"; 305*4882a593Smuzhiyun #address-cells = <0x1>; 306*4882a593Smuzhiyun #size-cells = <0x0>; 307*4882a593Smuzhiyun reg = <0xe14 0x8>; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun phy1: ethernet-phy@1 { 310*4882a593Smuzhiyun max-speed = <100>; 311*4882a593Smuzhiyun reg = <0x1>; 312*4882a593Smuzhiyun compatible = "brcm,40nm-ephy", 313*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun }; 316*4882a593Smuzhiyun }; 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun ehci0: usb@480300 { 319*4882a593Smuzhiyun compatible = "brcm,bcm7346-ehci", "generic-ehci"; 320*4882a593Smuzhiyun reg = <0x480300 0x100>; 321*4882a593Smuzhiyun native-endian; 322*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 323*4882a593Smuzhiyun interrupts = <68>; 324*4882a593Smuzhiyun status = "disabled"; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun ohci0: usb@480400 { 328*4882a593Smuzhiyun compatible = "brcm,bcm7346-ohci", "generic-ohci"; 329*4882a593Smuzhiyun reg = <0x480400 0x100>; 330*4882a593Smuzhiyun native-endian; 331*4882a593Smuzhiyun no-big-frame-no; 332*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 333*4882a593Smuzhiyun interrupts = <70>; 334*4882a593Smuzhiyun status = "disabled"; 335*4882a593Smuzhiyun }; 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun ehci1: usb@480500 { 338*4882a593Smuzhiyun compatible = "brcm,bcm7346-ehci", "generic-ehci"; 339*4882a593Smuzhiyun reg = <0x480500 0x100>; 340*4882a593Smuzhiyun native-endian; 341*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 342*4882a593Smuzhiyun interrupts = <69>; 343*4882a593Smuzhiyun status = "disabled"; 344*4882a593Smuzhiyun }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun ohci1: usb@480600 { 347*4882a593Smuzhiyun compatible = "brcm,bcm7346-ohci", "generic-ohci"; 348*4882a593Smuzhiyun reg = <0x480600 0x100>; 349*4882a593Smuzhiyun native-endian; 350*4882a593Smuzhiyun no-big-frame-no; 351*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 352*4882a593Smuzhiyun interrupts = <71>; 353*4882a593Smuzhiyun status = "disabled"; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun ehci2: usb@490300 { 357*4882a593Smuzhiyun compatible = "brcm,bcm7346-ehci", "generic-ehci"; 358*4882a593Smuzhiyun reg = <0x490300 0x100>; 359*4882a593Smuzhiyun native-endian; 360*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 361*4882a593Smuzhiyun interrupts = <73>; 362*4882a593Smuzhiyun status = "disabled"; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun ohci2: usb@490400 { 366*4882a593Smuzhiyun compatible = "brcm,bcm7346-ohci", "generic-ohci"; 367*4882a593Smuzhiyun reg = <0x490400 0x100>; 368*4882a593Smuzhiyun native-endian; 369*4882a593Smuzhiyun no-big-frame-no; 370*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 371*4882a593Smuzhiyun interrupts = <75>; 372*4882a593Smuzhiyun status = "disabled"; 373*4882a593Smuzhiyun }; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun ehci3: usb@490500 { 376*4882a593Smuzhiyun compatible = "brcm,bcm7346-ehci", "generic-ehci"; 377*4882a593Smuzhiyun reg = <0x490500 0x100>; 378*4882a593Smuzhiyun native-endian; 379*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 380*4882a593Smuzhiyun interrupts = <74>; 381*4882a593Smuzhiyun status = "disabled"; 382*4882a593Smuzhiyun }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun ohci3: usb@490600 { 385*4882a593Smuzhiyun compatible = "brcm,bcm7346-ohci", "generic-ohci"; 386*4882a593Smuzhiyun reg = <0x490600 0x100>; 387*4882a593Smuzhiyun native-endian; 388*4882a593Smuzhiyun no-big-frame-no; 389*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 390*4882a593Smuzhiyun interrupts = <76>; 391*4882a593Smuzhiyun status = "disabled"; 392*4882a593Smuzhiyun }; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun hif_l2_intc: interrupt-controller@411000 { 395*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 396*4882a593Smuzhiyun reg = <0x411000 0x30>; 397*4882a593Smuzhiyun interrupt-controller; 398*4882a593Smuzhiyun #interrupt-cells = <1>; 399*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 400*4882a593Smuzhiyun interrupts = <30>; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun nand: nand@412800 { 404*4882a593Smuzhiyun compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand"; 405*4882a593Smuzhiyun #address-cells = <1>; 406*4882a593Smuzhiyun #size-cells = <0>; 407*4882a593Smuzhiyun reg-names = "nand"; 408*4882a593Smuzhiyun reg = <0x412800 0x400>; 409*4882a593Smuzhiyun interrupt-parent = <&hif_l2_intc>; 410*4882a593Smuzhiyun interrupts = <24>; 411*4882a593Smuzhiyun status = "disabled"; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun sata: sata@181000 { 415*4882a593Smuzhiyun compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci"; 416*4882a593Smuzhiyun reg-names = "ahci", "top-ctrl"; 417*4882a593Smuzhiyun reg = <0x181000 0xa9c>, <0x180020 0x1c>; 418*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 419*4882a593Smuzhiyun interrupts = <40>; 420*4882a593Smuzhiyun #address-cells = <1>; 421*4882a593Smuzhiyun #size-cells = <0>; 422*4882a593Smuzhiyun status = "disabled"; 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun sata0: sata-port@0 { 425*4882a593Smuzhiyun reg = <0>; 426*4882a593Smuzhiyun phys = <&sata_phy0>; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun sata1: sata-port@1 { 430*4882a593Smuzhiyun reg = <1>; 431*4882a593Smuzhiyun phys = <&sata_phy1>; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun sata_phy: sata-phy@180100 { 436*4882a593Smuzhiyun compatible = "brcm,bcm7425-sata-phy", "brcm,phy-sata3"; 437*4882a593Smuzhiyun reg = <0x180100 0x0eff>; 438*4882a593Smuzhiyun reg-names = "phy"; 439*4882a593Smuzhiyun #address-cells = <1>; 440*4882a593Smuzhiyun #size-cells = <0>; 441*4882a593Smuzhiyun status = "disabled"; 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun sata_phy0: sata-phy@0 { 444*4882a593Smuzhiyun reg = <0>; 445*4882a593Smuzhiyun #phy-cells = <0>; 446*4882a593Smuzhiyun }; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun sata_phy1: sata-phy@1 { 449*4882a593Smuzhiyun reg = <1>; 450*4882a593Smuzhiyun #phy-cells = <0>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun sdhci0: sdhci@413500 { 455*4882a593Smuzhiyun compatible = "brcm,bcm7425-sdhci"; 456*4882a593Smuzhiyun reg = <0x413500 0x100>; 457*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 458*4882a593Smuzhiyun interrupts = <85>; 459*4882a593Smuzhiyun status = "disabled"; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun spi_l2_intc: interrupt-controller@411d00 { 463*4882a593Smuzhiyun compatible = "brcm,l2-intc"; 464*4882a593Smuzhiyun reg = <0x411d00 0x30>; 465*4882a593Smuzhiyun interrupt-controller; 466*4882a593Smuzhiyun #interrupt-cells = <1>; 467*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 468*4882a593Smuzhiyun interrupts = <31>; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun qspi: spi@413000 { 472*4882a593Smuzhiyun #address-cells = <0x1>; 473*4882a593Smuzhiyun #size-cells = <0x0>; 474*4882a593Smuzhiyun compatible = "brcm,spi-bcm-qspi", 475*4882a593Smuzhiyun "brcm,spi-brcmstb-qspi"; 476*4882a593Smuzhiyun clocks = <&upg_clk>; 477*4882a593Smuzhiyun reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>; 478*4882a593Smuzhiyun reg-names = "cs_reg", "hif_mspi", "bspi"; 479*4882a593Smuzhiyun interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>; 480*4882a593Smuzhiyun interrupt-parent = <&spi_l2_intc>; 481*4882a593Smuzhiyun interrupt-names = "spi_lr_fullness_reached", 482*4882a593Smuzhiyun "spi_lr_session_aborted", 483*4882a593Smuzhiyun "spi_lr_impatient", 484*4882a593Smuzhiyun "spi_lr_session_done", 485*4882a593Smuzhiyun "spi_lr_overread", 486*4882a593Smuzhiyun "mspi_done", 487*4882a593Smuzhiyun "mspi_halted"; 488*4882a593Smuzhiyun status = "disabled"; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun mspi: spi@408a00 { 492*4882a593Smuzhiyun #address-cells = <1>; 493*4882a593Smuzhiyun #size-cells = <0>; 494*4882a593Smuzhiyun compatible = "brcm,spi-bcm-qspi", 495*4882a593Smuzhiyun "brcm,spi-brcmstb-mspi"; 496*4882a593Smuzhiyun clocks = <&upg_clk>; 497*4882a593Smuzhiyun reg = <0x408a00 0x180>; 498*4882a593Smuzhiyun reg-names = "mspi"; 499*4882a593Smuzhiyun interrupts = <0x14>; 500*4882a593Smuzhiyun interrupt-parent = <&upg_aon_irq0_intc>; 501*4882a593Smuzhiyun interrupt-names = "mspi_done"; 502*4882a593Smuzhiyun status = "disabled"; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun waketimer: waketimer@408e80 { 506*4882a593Smuzhiyun compatible = "brcm,brcmstb-waketimer"; 507*4882a593Smuzhiyun reg = <0x408e80 0x14>; 508*4882a593Smuzhiyun interrupts = <0x3>; 509*4882a593Smuzhiyun interrupt-parent = <&aon_pm_l2_intc>; 510*4882a593Smuzhiyun interrupt-names = "timer"; 511*4882a593Smuzhiyun clocks = <&upg_clk>; 512*4882a593Smuzhiyun status = "disabled"; 513*4882a593Smuzhiyun }; 514*4882a593Smuzhiyun }; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun memory_controllers { 517*4882a593Smuzhiyun compatible = "simple-bus"; 518*4882a593Smuzhiyun ranges = <0x0 0x103b0000 0xa000>; 519*4882a593Smuzhiyun #address-cells = <1>; 520*4882a593Smuzhiyun #size-cells = <1>; 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun memory-controller@0 { 523*4882a593Smuzhiyun compatible = "brcm,brcmstb-memc", "simple-bus"; 524*4882a593Smuzhiyun ranges = <0x0 0x0 0xa000>; 525*4882a593Smuzhiyun #address-cells = <1>; 526*4882a593Smuzhiyun #size-cells = <1>; 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun memc-arb@1000 { 529*4882a593Smuzhiyun compatible = "brcm,brcmstb-memc-arb"; 530*4882a593Smuzhiyun reg = <0x1000 0x248>; 531*4882a593Smuzhiyun }; 532*4882a593Smuzhiyun 533*4882a593Smuzhiyun memc-ddr@2000 { 534*4882a593Smuzhiyun compatible = "brcm,brcmstb-memc-ddr"; 535*4882a593Smuzhiyun reg = <0x2000 0x300>; 536*4882a593Smuzhiyun }; 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun ddr-phy@6000 { 539*4882a593Smuzhiyun compatible = "brcm,brcmstb-ddr-phy"; 540*4882a593Smuzhiyun reg = <0x6000 0xc8>; 541*4882a593Smuzhiyun }; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun shimphy@8000 { 544*4882a593Smuzhiyun compatible = "brcm,brcmstb-ddr-shimphy"; 545*4882a593Smuzhiyun reg = <0x8000 0x13c>; 546*4882a593Smuzhiyun }; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun}; 550