xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/brcm/bcm63268.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/ {
3*4882a593Smuzhiyun	#address-cells = <1>;
4*4882a593Smuzhiyun	#size-cells = <1>;
5*4882a593Smuzhiyun	compatible = "brcm,bcm63268";
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun	cpus {
8*4882a593Smuzhiyun		#address-cells = <1>;
9*4882a593Smuzhiyun		#size-cells = <0>;
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun		mips-hpt-frequency = <200000000>;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun		cpu@0 {
14*4882a593Smuzhiyun			compatible = "brcm,bmips4350";
15*4882a593Smuzhiyun			device_type = "cpu";
16*4882a593Smuzhiyun			reg = <0>;
17*4882a593Smuzhiyun		};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun		cpu@1 {
20*4882a593Smuzhiyun			compatible = "brcm,bmips4350";
21*4882a593Smuzhiyun			device_type = "cpu";
22*4882a593Smuzhiyun			reg = <1>;
23*4882a593Smuzhiyun		};
24*4882a593Smuzhiyun	};
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	clocks {
27*4882a593Smuzhiyun		periph_clk: periph-clk {
28*4882a593Smuzhiyun			compatible = "fixed-clock";
29*4882a593Smuzhiyun			#clock-cells = <0>;
30*4882a593Smuzhiyun			clock-frequency = <50000000>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	aliases {
35*4882a593Smuzhiyun		serial0 = &uart0;
36*4882a593Smuzhiyun		serial1 = &uart1;
37*4882a593Smuzhiyun	};
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun	cpu_intc: interrupt-controller {
40*4882a593Smuzhiyun		#address-cells = <0>;
41*4882a593Smuzhiyun		compatible = "mti,cpu-interrupt-controller";
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun		interrupt-controller;
44*4882a593Smuzhiyun		#interrupt-cells = <1>;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	ubus {
48*4882a593Smuzhiyun		#address-cells = <1>;
49*4882a593Smuzhiyun		#size-cells = <1>;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun		compatible = "simple-bus";
52*4882a593Smuzhiyun		ranges;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		clkctl: clock-controller@10000004 {
55*4882a593Smuzhiyun			compatible = "brcm,bcm63268-clocks";
56*4882a593Smuzhiyun			reg = <0x10000004 0x4>;
57*4882a593Smuzhiyun			#clock-cells = <1>;
58*4882a593Smuzhiyun		};
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun		periph_cntl: syscon@10000008 {
61*4882a593Smuzhiyun			compatible = "syscon";
62*4882a593Smuzhiyun			reg = <0x10000008 0x4>;
63*4882a593Smuzhiyun			native-endian;
64*4882a593Smuzhiyun		};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun		reboot: syscon-reboot@10000008 {
67*4882a593Smuzhiyun			compatible = "syscon-reboot";
68*4882a593Smuzhiyun			regmap = <&periph_cntl>;
69*4882a593Smuzhiyun			offset = <0x0>;
70*4882a593Smuzhiyun			mask = <0x1>;
71*4882a593Smuzhiyun		};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun		periph_intc: interrupt-controller@10000020 {
74*4882a593Smuzhiyun			compatible = "brcm,bcm6345-l1-intc";
75*4882a593Smuzhiyun			reg = <0x10000020 0x20>,
76*4882a593Smuzhiyun			      <0x10000040 0x20>;
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun			interrupt-controller;
79*4882a593Smuzhiyun			#interrupt-cells = <1>;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun			interrupt-parent = <&cpu_intc>;
82*4882a593Smuzhiyun			interrupts = <2>, <3>;
83*4882a593Smuzhiyun		};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun		uart0: serial@10000180 {
86*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
87*4882a593Smuzhiyun			reg = <0x10000180 0x18>;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
90*4882a593Smuzhiyun			interrupts = <5>;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun			clocks = <&periph_clk>;
93*4882a593Smuzhiyun			clock-names = "refclk";
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun			status = "disabled";
96*4882a593Smuzhiyun		};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun		uart1: serial@100001a0 {
99*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
100*4882a593Smuzhiyun			reg = <0x100001a0 0x18>;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
103*4882a593Smuzhiyun			interrupts = <34>;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun			clocks = <&periph_clk>;
106*4882a593Smuzhiyun			clock-names = "refclk";
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun			status = "disabled";
109*4882a593Smuzhiyun		};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun		leds0: led-controller@10001900 {
112*4882a593Smuzhiyun			#address-cells = <1>;
113*4882a593Smuzhiyun			#size-cells = <0>;
114*4882a593Smuzhiyun			compatible = "brcm,bcm6328-leds";
115*4882a593Smuzhiyun			reg = <0x10001900 0x24>;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			status = "disabled";
118*4882a593Smuzhiyun		};
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun		periph_pwr: power-controller@1000184c {
121*4882a593Smuzhiyun			compatible = "brcm,bcm6328-power-controller";
122*4882a593Smuzhiyun			reg = <0x1000184c 0x4>;
123*4882a593Smuzhiyun			#power-domain-cells = <1>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun		ehci: usb@10002500 {
127*4882a593Smuzhiyun			compatible = "brcm,bcm63268-ehci", "generic-ehci";
128*4882a593Smuzhiyun			reg = <0x10002500 0x100>;
129*4882a593Smuzhiyun			big-endian;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
132*4882a593Smuzhiyun			interrupts = <10>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			status = "disabled";
135*4882a593Smuzhiyun		};
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun		ohci: usb@10002600 {
138*4882a593Smuzhiyun			compatible = "brcm,bcm63268-ohci", "generic-ohci";
139*4882a593Smuzhiyun			reg = <0x10002600 0x100>;
140*4882a593Smuzhiyun			big-endian;
141*4882a593Smuzhiyun			no-big-frame-no;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
144*4882a593Smuzhiyun			interrupts = <9>;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun			status = "disabled";
147*4882a593Smuzhiyun		};
148*4882a593Smuzhiyun	};
149*4882a593Smuzhiyun};
150