xref: /OK3568_Linux_fs/kernel/arch/mips/boot/dts/brcm/bcm3384_zephyr.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun/ {
3*4882a593Smuzhiyun	#address-cells = <1>;
4*4882a593Smuzhiyun	#size-cells = <1>;
5*4882a593Smuzhiyun	compatible = "brcm,bcm3384", "brcm,bcm33843";
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun	memory@0 {
8*4882a593Smuzhiyun		device_type = "memory";
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun		/* Typical range.  The bootloader should fill this in. */
11*4882a593Smuzhiyun		reg = <0x0 0x08000000>;
12*4882a593Smuzhiyun	};
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun	cpus {
15*4882a593Smuzhiyun		#address-cells = <1>;
16*4882a593Smuzhiyun		#size-cells = <0>;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun		/* On BMIPS5000 this is 1/8th of the CPU core clock */
19*4882a593Smuzhiyun		mips-hpt-frequency = <100000000>;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun		cpu@0 {
22*4882a593Smuzhiyun			compatible = "brcm,bmips5000";
23*4882a593Smuzhiyun			device_type = "cpu";
24*4882a593Smuzhiyun			reg = <0>;
25*4882a593Smuzhiyun		};
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun		cpu@1 {
28*4882a593Smuzhiyun			compatible = "brcm,bmips5000";
29*4882a593Smuzhiyun			device_type = "cpu";
30*4882a593Smuzhiyun			reg = <1>;
31*4882a593Smuzhiyun		};
32*4882a593Smuzhiyun	};
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun	cpu_intc: cpu_intc {
35*4882a593Smuzhiyun		#address-cells = <0>;
36*4882a593Smuzhiyun		compatible = "mti,cpu-interrupt-controller";
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun		interrupt-controller;
39*4882a593Smuzhiyun		#interrupt-cells = <1>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	clocks {
43*4882a593Smuzhiyun		periph_clk: periph_clk {
44*4882a593Smuzhiyun			compatible = "fixed-clock";
45*4882a593Smuzhiyun			#clock-cells = <0>;
46*4882a593Smuzhiyun			clock-frequency = <54000000>;
47*4882a593Smuzhiyun		};
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	aliases {
51*4882a593Smuzhiyun		uart0 = &uart0;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	ubus {
55*4882a593Smuzhiyun		#address-cells = <1>;
56*4882a593Smuzhiyun		#size-cells = <1>;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun		compatible = "brcm,ubus", "simple-bus";
59*4882a593Smuzhiyun		ranges;
60*4882a593Smuzhiyun		dma-ranges = <0x00000000 0x08000000 0x08000000>,
61*4882a593Smuzhiyun			     <0x08000000 0x00000000 0x08000000>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		periph_intc: periph_intc@14e00038 {
64*4882a593Smuzhiyun			compatible = "brcm,bcm3380-l2-intc";
65*4882a593Smuzhiyun			reg = <0x14e00038 0x4 0x14e0003c 0x4>,
66*4882a593Smuzhiyun			      <0x14e00340 0x4 0x14e00344 0x4>;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun			interrupt-controller;
69*4882a593Smuzhiyun			#interrupt-cells = <1>;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun			interrupt-parent = <&cpu_intc>;
72*4882a593Smuzhiyun			interrupts = <4>;
73*4882a593Smuzhiyun		};
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun		zmips_intc: zmips_intc@104b0060 {
76*4882a593Smuzhiyun			compatible = "brcm,bcm3380-l2-intc";
77*4882a593Smuzhiyun			reg = <0x104b0060 0x4 0x104b0064 0x4>;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun			interrupt-controller;
80*4882a593Smuzhiyun			#interrupt-cells = <1>;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
83*4882a593Smuzhiyun			interrupts = <29>;
84*4882a593Smuzhiyun			brcm,int-map-mask = <0xffffffff>;
85*4882a593Smuzhiyun		};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun		iop_intc: iop_intc@14e00058 {
88*4882a593Smuzhiyun			compatible = "brcm,bcm3380-l2-intc";
89*4882a593Smuzhiyun			reg = <0x14e00058 0x4 0x14e0005c 0x4>;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun			interrupt-controller;
92*4882a593Smuzhiyun			#interrupt-cells = <1>;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun			interrupt-parent = <&cpu_intc>;
95*4882a593Smuzhiyun			interrupts = <6>;
96*4882a593Smuzhiyun			brcm,int-map-mask = <0xffffffff>;
97*4882a593Smuzhiyun		};
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun		uart0: serial@14e00520 {
100*4882a593Smuzhiyun			compatible = "brcm,bcm6345-uart";
101*4882a593Smuzhiyun			reg = <0x14e00520 0x18>;
102*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
103*4882a593Smuzhiyun			interrupts = <2>;
104*4882a593Smuzhiyun			clocks = <&periph_clk>;
105*4882a593Smuzhiyun			status = "disabled";
106*4882a593Smuzhiyun		};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun		ehci0: usb@15400300 {
109*4882a593Smuzhiyun			compatible = "brcm,bcm3384-ehci", "generic-ehci";
110*4882a593Smuzhiyun			reg = <0x15400300 0x100>;
111*4882a593Smuzhiyun			big-endian;
112*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
113*4882a593Smuzhiyun			interrupts = <41>;
114*4882a593Smuzhiyun			status = "disabled";
115*4882a593Smuzhiyun		};
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		ohci0: usb@15400400 {
118*4882a593Smuzhiyun			compatible = "brcm,bcm3384-ohci", "generic-ohci";
119*4882a593Smuzhiyun			reg = <0x15400400 0x100>;
120*4882a593Smuzhiyun			big-endian;
121*4882a593Smuzhiyun			no-big-frame-no;
122*4882a593Smuzhiyun			interrupt-parent = <&periph_intc>;
123*4882a593Smuzhiyun			interrupts = <40>;
124*4882a593Smuzhiyun			status = "disabled";
125*4882a593Smuzhiyun		};
126*4882a593Smuzhiyun	};
127*4882a593Smuzhiyun};
128