1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/ { 3*4882a593Smuzhiyun #address-cells = <1>; 4*4882a593Smuzhiyun #size-cells = <1>; 5*4882a593Smuzhiyun compatible = "brcm,bcm3368"; 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun cpus { 8*4882a593Smuzhiyun #address-cells = <1>; 9*4882a593Smuzhiyun #size-cells = <0>; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun mips-hpt-frequency = <150000000>; 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun cpu@0 { 14*4882a593Smuzhiyun compatible = "brcm,bmips4350"; 15*4882a593Smuzhiyun device_type = "cpu"; 16*4882a593Smuzhiyun reg = <0>; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun cpu@1 { 20*4882a593Smuzhiyun compatible = "brcm,bmips4350"; 21*4882a593Smuzhiyun device_type = "cpu"; 22*4882a593Smuzhiyun reg = <1>; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks { 27*4882a593Smuzhiyun periph_clk: periph-clk { 28*4882a593Smuzhiyun compatible = "fixed-clock"; 29*4882a593Smuzhiyun #clock-cells = <0>; 30*4882a593Smuzhiyun clock-frequency = <50000000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun aliases { 35*4882a593Smuzhiyun serial0 = &uart0; 36*4882a593Smuzhiyun serial1 = &uart1; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpu_intc: interrupt-controller { 40*4882a593Smuzhiyun #address-cells = <0>; 41*4882a593Smuzhiyun compatible = "mti,cpu-interrupt-controller"; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun interrupt-controller; 44*4882a593Smuzhiyun #interrupt-cells = <1>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun ubus { 48*4882a593Smuzhiyun #address-cells = <1>; 49*4882a593Smuzhiyun #size-cells = <1>; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun compatible = "simple-bus"; 52*4882a593Smuzhiyun ranges; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clkctl: clock-controller@fff8c004 { 55*4882a593Smuzhiyun compatible = "brcm,bcm3368-clocks"; 56*4882a593Smuzhiyun reg = <0xfff8c004 0x4>; 57*4882a593Smuzhiyun #clock-cells = <1>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun periph_cntl: syscon@fff8c008 { 61*4882a593Smuzhiyun compatible = "syscon"; 62*4882a593Smuzhiyun reg = <0xfff8c008 0x4>; 63*4882a593Smuzhiyun native-endian; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reboot: syscon-reboot@fff8c008 { 67*4882a593Smuzhiyun compatible = "syscon-reboot"; 68*4882a593Smuzhiyun regmap = <&periph_cntl>; 69*4882a593Smuzhiyun offset = <0x0>; 70*4882a593Smuzhiyun mask = <0x1>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun periph_intc: interrupt-controller@fff8c00c { 74*4882a593Smuzhiyun compatible = "brcm,bcm6345-l1-intc"; 75*4882a593Smuzhiyun reg = <0xfff8c00c 0x8>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun interrupt-controller; 78*4882a593Smuzhiyun #interrupt-cells = <1>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun interrupt-parent = <&cpu_intc>; 81*4882a593Smuzhiyun interrupts = <2>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun uart0: serial@fff8c100 { 85*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 86*4882a593Smuzhiyun reg = <0xfff8c100 0x18>; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 89*4882a593Smuzhiyun interrupts = <2>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun clocks = <&periph_clk>; 92*4882a593Smuzhiyun clock-names = "refclk"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun status = "disabled"; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun uart1: serial@fff8c120 { 98*4882a593Smuzhiyun compatible = "brcm,bcm6345-uart"; 99*4882a593Smuzhiyun reg = <0xfff8c120 0x18>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun interrupt-parent = <&periph_intc>; 102*4882a593Smuzhiyun interrupts = <3>; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun clocks = <&periph_clk>; 105*4882a593Smuzhiyun clock-names = "refclk"; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun status = "disabled"; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun}; 111