xref: /OK3568_Linux_fs/kernel/arch/mips/bcm63xx/setup.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun  * License.  See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun  * for more details.
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/memblock.h>
13*4882a593Smuzhiyun #include <linux/ioport.h>
14*4882a593Smuzhiyun #include <linux/pm.h>
15*4882a593Smuzhiyun #include <asm/bootinfo.h>
16*4882a593Smuzhiyun #include <asm/time.h>
17*4882a593Smuzhiyun #include <asm/reboot.h>
18*4882a593Smuzhiyun #include <asm/cacheflush.h>
19*4882a593Smuzhiyun #include <bcm63xx_board.h>
20*4882a593Smuzhiyun #include <bcm63xx_cpu.h>
21*4882a593Smuzhiyun #include <bcm63xx_regs.h>
22*4882a593Smuzhiyun #include <bcm63xx_io.h>
23*4882a593Smuzhiyun #include <bcm63xx_gpio.h>
24*4882a593Smuzhiyun 
bcm63xx_machine_halt(void)25*4882a593Smuzhiyun void bcm63xx_machine_halt(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun 	pr_info("System halted\n");
28*4882a593Smuzhiyun 	while (1)
29*4882a593Smuzhiyun 		;
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun 
bcm6348_a1_reboot(void)32*4882a593Smuzhiyun static void bcm6348_a1_reboot(void)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun 	u32 reg;
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	/* soft reset all blocks */
37*4882a593Smuzhiyun 	pr_info("soft-resetting all blocks ...\n");
38*4882a593Smuzhiyun 	reg = bcm_perf_readl(PERF_SOFTRESET_REG);
39*4882a593Smuzhiyun 	reg &= ~SOFTRESET_6348_ALL;
40*4882a593Smuzhiyun 	bcm_perf_writel(reg, PERF_SOFTRESET_REG);
41*4882a593Smuzhiyun 	mdelay(10);
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun 	reg = bcm_perf_readl(PERF_SOFTRESET_REG);
44*4882a593Smuzhiyun 	reg |= SOFTRESET_6348_ALL;
45*4882a593Smuzhiyun 	bcm_perf_writel(reg, PERF_SOFTRESET_REG);
46*4882a593Smuzhiyun 	mdelay(10);
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/* Jump to the power on address. */
49*4882a593Smuzhiyun 	pr_info("jumping to reset vector.\n");
50*4882a593Smuzhiyun 	/* set high vectors (base at 0xbfc00000 */
51*4882a593Smuzhiyun 	set_c0_status(ST0_BEV | ST0_ERL);
52*4882a593Smuzhiyun 	/* run uncached in kseg0 */
53*4882a593Smuzhiyun 	change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
54*4882a593Smuzhiyun 	__flush_cache_all();
55*4882a593Smuzhiyun 	/* remove all wired TLB entries */
56*4882a593Smuzhiyun 	write_c0_wired(0);
57*4882a593Smuzhiyun 	__asm__ __volatile__(
58*4882a593Smuzhiyun 		"jr\t%0"
59*4882a593Smuzhiyun 		:
60*4882a593Smuzhiyun 		: "r" (0xbfc00000));
61*4882a593Smuzhiyun 	while (1)
62*4882a593Smuzhiyun 		;
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun 
bcm63xx_machine_reboot(void)65*4882a593Smuzhiyun void bcm63xx_machine_reboot(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun 	u32 reg, perf_regs[2] = { 0, 0 };
68*4882a593Smuzhiyun 	unsigned int i;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 	/* mask and clear all external irq */
71*4882a593Smuzhiyun 	switch (bcm63xx_get_cpu_id()) {
72*4882a593Smuzhiyun 	case BCM3368_CPU_ID:
73*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
74*4882a593Smuzhiyun 		break;
75*4882a593Smuzhiyun 	case BCM6328_CPU_ID:
76*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
77*4882a593Smuzhiyun 		break;
78*4882a593Smuzhiyun 	case BCM6338_CPU_ID:
79*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
80*4882a593Smuzhiyun 		break;
81*4882a593Smuzhiyun 	case BCM6345_CPU_ID:
82*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6345;
83*4882a593Smuzhiyun 		break;
84*4882a593Smuzhiyun 	case BCM6348_CPU_ID:
85*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6348;
86*4882a593Smuzhiyun 		break;
87*4882a593Smuzhiyun 	case BCM6358_CPU_ID:
88*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
89*4882a593Smuzhiyun 		break;
90*4882a593Smuzhiyun 	case BCM6362_CPU_ID:
91*4882a593Smuzhiyun 		perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
92*4882a593Smuzhiyun 		break;
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	for (i = 0; i < 2; i++) {
96*4882a593Smuzhiyun 		if (!perf_regs[i])
97*4882a593Smuzhiyun 			break;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 		reg = bcm_perf_readl(perf_regs[i]);
100*4882a593Smuzhiyun 		if (BCMCPU_IS_6348()) {
101*4882a593Smuzhiyun 			reg &= ~EXTIRQ_CFG_MASK_ALL_6348;
102*4882a593Smuzhiyun 			reg |= EXTIRQ_CFG_CLEAR_ALL_6348;
103*4882a593Smuzhiyun 		} else {
104*4882a593Smuzhiyun 			reg &= ~EXTIRQ_CFG_MASK_ALL;
105*4882a593Smuzhiyun 			reg |= EXTIRQ_CFG_CLEAR_ALL;
106*4882a593Smuzhiyun 		}
107*4882a593Smuzhiyun 		bcm_perf_writel(reg, perf_regs[i]);
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1))
111*4882a593Smuzhiyun 		bcm6348_a1_reboot();
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	pr_info("triggering watchdog soft-reset...\n");
114*4882a593Smuzhiyun 	if (BCMCPU_IS_6328()) {
115*4882a593Smuzhiyun 		bcm_wdt_writel(1, WDT_SOFTRESET_REG);
116*4882a593Smuzhiyun 	} else {
117*4882a593Smuzhiyun 		reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
118*4882a593Smuzhiyun 		reg |= SYS_PLL_SOFT_RESET;
119*4882a593Smuzhiyun 		bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
120*4882a593Smuzhiyun 	}
121*4882a593Smuzhiyun 	while (1)
122*4882a593Smuzhiyun 		;
123*4882a593Smuzhiyun }
124*4882a593Smuzhiyun 
__bcm63xx_machine_reboot(char * p)125*4882a593Smuzhiyun static void __bcm63xx_machine_reboot(char *p)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	bcm63xx_machine_reboot();
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /*
131*4882a593Smuzhiyun  * return system type in /proc/cpuinfo
132*4882a593Smuzhiyun  */
get_system_type(void)133*4882a593Smuzhiyun const char *get_system_type(void)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	static char buf[128];
136*4882a593Smuzhiyun 	snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%02X)",
137*4882a593Smuzhiyun 		 board_get_name(),
138*4882a593Smuzhiyun 		 bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev());
139*4882a593Smuzhiyun 	return buf;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
plat_time_init(void)142*4882a593Smuzhiyun void __init plat_time_init(void)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
plat_mem_setup(void)147*4882a593Smuzhiyun void __init plat_mem_setup(void)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun 	memblock_add(0, bcm63xx_get_memory_size());
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	_machine_halt = bcm63xx_machine_halt;
152*4882a593Smuzhiyun 	_machine_restart = __bcm63xx_machine_reboot;
153*4882a593Smuzhiyun 	pm_power_off = bcm63xx_machine_halt;
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	set_io_port_base(0);
156*4882a593Smuzhiyun 	ioport_resource.start = 0;
157*4882a593Smuzhiyun 	ioport_resource.end = ~0;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	board_setup();
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun 
bcm63xx_register_devices(void)162*4882a593Smuzhiyun int __init bcm63xx_register_devices(void)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	/* register gpiochip */
165*4882a593Smuzhiyun 	bcm63xx_gpio_init();
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	return board_register_devices();
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun arch_initcall(bcm63xx_register_devices);
171