1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive 4*4882a593Smuzhiyun * for more details. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/init.h> 10*4882a593Smuzhiyun #include <linux/memblock.h> 11*4882a593Smuzhiyun #include <linux/smp.h> 12*4882a593Smuzhiyun #include <asm/bootinfo.h> 13*4882a593Smuzhiyun #include <asm/bmips.h> 14*4882a593Smuzhiyun #include <asm/smp-ops.h> 15*4882a593Smuzhiyun #include <asm/mipsregs.h> 16*4882a593Smuzhiyun #include <bcm63xx_board.h> 17*4882a593Smuzhiyun #include <bcm63xx_cpu.h> 18*4882a593Smuzhiyun #include <bcm63xx_io.h> 19*4882a593Smuzhiyun #include <bcm63xx_regs.h> 20*4882a593Smuzhiyun prom_init(void)21*4882a593Smuzhiyunvoid __init prom_init(void) 22*4882a593Smuzhiyun { 23*4882a593Smuzhiyun u32 reg, mask; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun bcm63xx_cpu_init(); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* stop any running watchdog */ 28*4882a593Smuzhiyun bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); 29*4882a593Smuzhiyun bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* disable all hardware blocks clock for now */ 32*4882a593Smuzhiyun if (BCMCPU_IS_3368()) 33*4882a593Smuzhiyun mask = CKCTL_3368_ALL_SAFE_EN; 34*4882a593Smuzhiyun else if (BCMCPU_IS_6328()) 35*4882a593Smuzhiyun mask = CKCTL_6328_ALL_SAFE_EN; 36*4882a593Smuzhiyun else if (BCMCPU_IS_6338()) 37*4882a593Smuzhiyun mask = CKCTL_6338_ALL_SAFE_EN; 38*4882a593Smuzhiyun else if (BCMCPU_IS_6345()) 39*4882a593Smuzhiyun mask = CKCTL_6345_ALL_SAFE_EN; 40*4882a593Smuzhiyun else if (BCMCPU_IS_6348()) 41*4882a593Smuzhiyun mask = CKCTL_6348_ALL_SAFE_EN; 42*4882a593Smuzhiyun else if (BCMCPU_IS_6358()) 43*4882a593Smuzhiyun mask = CKCTL_6358_ALL_SAFE_EN; 44*4882a593Smuzhiyun else if (BCMCPU_IS_6362()) 45*4882a593Smuzhiyun mask = CKCTL_6362_ALL_SAFE_EN; 46*4882a593Smuzhiyun else if (BCMCPU_IS_6368()) 47*4882a593Smuzhiyun mask = CKCTL_6368_ALL_SAFE_EN; 48*4882a593Smuzhiyun else 49*4882a593Smuzhiyun mask = 0; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun reg = bcm_perf_readl(PERF_CKCTL_REG); 52*4882a593Smuzhiyun reg &= ~mask; 53*4882a593Smuzhiyun bcm_perf_writel(reg, PERF_CKCTL_REG); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* do low level board init */ 56*4882a593Smuzhiyun board_prom_init(); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* set up SMP */ 59*4882a593Smuzhiyun if (!register_bmips_smp_ops()) { 60*4882a593Smuzhiyun /* 61*4882a593Smuzhiyun * BCM6328 might not have its second CPU enabled, while BCM3368 62*4882a593Smuzhiyun * and BCM6358 need special handling for their shared TLB, so 63*4882a593Smuzhiyun * disable SMP for now. 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun if (BCMCPU_IS_6328()) { 66*4882a593Smuzhiyun reg = bcm_readl(BCM_6328_OTP_BASE + 67*4882a593Smuzhiyun OTP_USER_BITS_6328_REG(3)); 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun if (reg & OTP_6328_REG3_TP1_DISABLED) 70*4882a593Smuzhiyun bmips_smp_enabled = 0; 71*4882a593Smuzhiyun } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) { 72*4882a593Smuzhiyun bmips_smp_enabled = 0; 73*4882a593Smuzhiyun } 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun if (!bmips_smp_enabled) 76*4882a593Smuzhiyun return; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * The bootloader has set up the CPU1 reset vector at 80*4882a593Smuzhiyun * 0xa000_0200. 81*4882a593Smuzhiyun * This conflicts with the special interrupt vector (IV). 82*4882a593Smuzhiyun * The bootloader has also set up CPU1 to respond to the wrong 83*4882a593Smuzhiyun * IPI interrupt. 84*4882a593Smuzhiyun * Here we will start up CPU1 in the background and ask it to 85*4882a593Smuzhiyun * reconfigure itself then go back to sleep. 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun memcpy((void *)0xa0000200, bmips_smp_movevec, 0x20); 88*4882a593Smuzhiyun __sync(); 89*4882a593Smuzhiyun set_c0_cause(C_SW0); 90*4882a593Smuzhiyun cpumask_set_cpu(1, &bmips_booted_mask); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * FIXME: we really should have some sort of hazard barrier here 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun } 96*4882a593Smuzhiyun } 97*4882a593Smuzhiyun prom_free_prom_memory(void)98*4882a593Smuzhiyunvoid __init prom_free_prom_memory(void) 99*4882a593Smuzhiyun { 100*4882a593Smuzhiyun } 101