1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
3*4882a593Smuzhiyun * License. See the file "COPYING" in the main directory of this archive
4*4882a593Smuzhiyun * for more details.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7*4882a593Smuzhiyun * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/spinlock.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/gpio/driver.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <bcm63xx_cpu.h>
17*4882a593Smuzhiyun #include <bcm63xx_gpio.h>
18*4882a593Smuzhiyun #include <bcm63xx_io.h>
19*4882a593Smuzhiyun #include <bcm63xx_regs.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun static u32 gpio_out_low_reg;
22*4882a593Smuzhiyun
bcm63xx_gpio_out_low_reg_init(void)23*4882a593Smuzhiyun static void bcm63xx_gpio_out_low_reg_init(void)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun switch (bcm63xx_get_cpu_id()) {
26*4882a593Smuzhiyun case BCM6345_CPU_ID:
27*4882a593Smuzhiyun gpio_out_low_reg = GPIO_DATA_LO_REG_6345;
28*4882a593Smuzhiyun break;
29*4882a593Smuzhiyun default:
30*4882a593Smuzhiyun gpio_out_low_reg = GPIO_DATA_LO_REG;
31*4882a593Smuzhiyun break;
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static DEFINE_SPINLOCK(bcm63xx_gpio_lock);
36*4882a593Smuzhiyun static u32 gpio_out_low, gpio_out_high;
37*4882a593Smuzhiyun
bcm63xx_gpio_set(struct gpio_chip * chip,unsigned gpio,int val)38*4882a593Smuzhiyun static void bcm63xx_gpio_set(struct gpio_chip *chip,
39*4882a593Smuzhiyun unsigned gpio, int val)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun u32 reg;
42*4882a593Smuzhiyun u32 mask;
43*4882a593Smuzhiyun u32 *v;
44*4882a593Smuzhiyun unsigned long flags;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun if (gpio >= chip->ngpio)
47*4882a593Smuzhiyun BUG();
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun if (gpio < 32) {
50*4882a593Smuzhiyun reg = gpio_out_low_reg;
51*4882a593Smuzhiyun mask = 1 << gpio;
52*4882a593Smuzhiyun v = &gpio_out_low;
53*4882a593Smuzhiyun } else {
54*4882a593Smuzhiyun reg = GPIO_DATA_HI_REG;
55*4882a593Smuzhiyun mask = 1 << (gpio - 32);
56*4882a593Smuzhiyun v = &gpio_out_high;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
60*4882a593Smuzhiyun if (val)
61*4882a593Smuzhiyun *v |= mask;
62*4882a593Smuzhiyun else
63*4882a593Smuzhiyun *v &= ~mask;
64*4882a593Smuzhiyun bcm_gpio_writel(*v, reg);
65*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
bcm63xx_gpio_get(struct gpio_chip * chip,unsigned gpio)68*4882a593Smuzhiyun static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun u32 reg;
71*4882a593Smuzhiyun u32 mask;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (gpio >= chip->ngpio)
74*4882a593Smuzhiyun BUG();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (gpio < 32) {
77*4882a593Smuzhiyun reg = gpio_out_low_reg;
78*4882a593Smuzhiyun mask = 1 << gpio;
79*4882a593Smuzhiyun } else {
80*4882a593Smuzhiyun reg = GPIO_DATA_HI_REG;
81*4882a593Smuzhiyun mask = 1 << (gpio - 32);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun return !!(bcm_gpio_readl(reg) & mask);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
bcm63xx_gpio_set_direction(struct gpio_chip * chip,unsigned gpio,int dir)87*4882a593Smuzhiyun static int bcm63xx_gpio_set_direction(struct gpio_chip *chip,
88*4882a593Smuzhiyun unsigned gpio, int dir)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun u32 reg;
91*4882a593Smuzhiyun u32 mask;
92*4882a593Smuzhiyun u32 tmp;
93*4882a593Smuzhiyun unsigned long flags;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (gpio >= chip->ngpio)
96*4882a593Smuzhiyun BUG();
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun if (gpio < 32) {
99*4882a593Smuzhiyun reg = GPIO_CTL_LO_REG;
100*4882a593Smuzhiyun mask = 1 << gpio;
101*4882a593Smuzhiyun } else {
102*4882a593Smuzhiyun reg = GPIO_CTL_HI_REG;
103*4882a593Smuzhiyun mask = 1 << (gpio - 32);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun spin_lock_irqsave(&bcm63xx_gpio_lock, flags);
107*4882a593Smuzhiyun tmp = bcm_gpio_readl(reg);
108*4882a593Smuzhiyun if (dir == BCM63XX_GPIO_DIR_IN)
109*4882a593Smuzhiyun tmp &= ~mask;
110*4882a593Smuzhiyun else
111*4882a593Smuzhiyun tmp |= mask;
112*4882a593Smuzhiyun bcm_gpio_writel(tmp, reg);
113*4882a593Smuzhiyun spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
bcm63xx_gpio_direction_input(struct gpio_chip * chip,unsigned gpio)118*4882a593Smuzhiyun static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_IN);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
bcm63xx_gpio_direction_output(struct gpio_chip * chip,unsigned gpio,int value)123*4882a593Smuzhiyun static int bcm63xx_gpio_direction_output(struct gpio_chip *chip,
124*4882a593Smuzhiyun unsigned gpio, int value)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun bcm63xx_gpio_set(chip, gpio, value);
127*4882a593Smuzhiyun return bcm63xx_gpio_set_direction(chip, gpio, BCM63XX_GPIO_DIR_OUT);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static struct gpio_chip bcm63xx_gpio_chip = {
132*4882a593Smuzhiyun .label = "bcm63xx-gpio",
133*4882a593Smuzhiyun .direction_input = bcm63xx_gpio_direction_input,
134*4882a593Smuzhiyun .direction_output = bcm63xx_gpio_direction_output,
135*4882a593Smuzhiyun .get = bcm63xx_gpio_get,
136*4882a593Smuzhiyun .set = bcm63xx_gpio_set,
137*4882a593Smuzhiyun .base = 0,
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
bcm63xx_gpio_init(void)140*4882a593Smuzhiyun int __init bcm63xx_gpio_init(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun bcm63xx_gpio_out_low_reg_init();
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun gpio_out_low = bcm_gpio_readl(gpio_out_low_reg);
145*4882a593Smuzhiyun if (!BCMCPU_IS_6345())
146*4882a593Smuzhiyun gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
147*4882a593Smuzhiyun bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
148*4882a593Smuzhiyun pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun return gpiochip_add_data(&bcm63xx_gpio_chip, NULL);
151*4882a593Smuzhiyun }
152