1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
5*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the
6*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your
7*4882a593Smuzhiyun * option) any later version.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along
21*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc.,
22*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include "bcm47xx_private.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/types.h>
28*4882a593Smuzhiyun #include <linux/interrupt.h>
29*4882a593Smuzhiyun #include <linux/irq.h>
30*4882a593Smuzhiyun #include <asm/setup.h>
31*4882a593Smuzhiyun #include <asm/irq_cpu.h>
32*4882a593Smuzhiyun #include <bcm47xx.h>
33*4882a593Smuzhiyun
plat_irq_dispatch(void)34*4882a593Smuzhiyun asmlinkage void plat_irq_dispatch(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun u32 cause;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun clear_c0_status(cause);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun if (cause & CAUSEF_IP7)
43*4882a593Smuzhiyun do_IRQ(7);
44*4882a593Smuzhiyun if (cause & CAUSEF_IP2)
45*4882a593Smuzhiyun do_IRQ(2);
46*4882a593Smuzhiyun if (cause & CAUSEF_IP3)
47*4882a593Smuzhiyun do_IRQ(3);
48*4882a593Smuzhiyun if (cause & CAUSEF_IP4)
49*4882a593Smuzhiyun do_IRQ(4);
50*4882a593Smuzhiyun if (cause & CAUSEF_IP5)
51*4882a593Smuzhiyun do_IRQ(5);
52*4882a593Smuzhiyun if (cause & CAUSEF_IP6)
53*4882a593Smuzhiyun do_IRQ(6);
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define DEFINE_HWx_IRQDISPATCH(x) \
57*4882a593Smuzhiyun static void bcm47xx_hw ## x ## _irqdispatch(void) \
58*4882a593Smuzhiyun { \
59*4882a593Smuzhiyun do_IRQ(x); \
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(2)
62*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(3)
63*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(4)
64*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(5)
65*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(6)
66*4882a593Smuzhiyun DEFINE_HWx_IRQDISPATCH(7)
67*4882a593Smuzhiyun
arch_init_irq(void)68*4882a593Smuzhiyun void __init arch_init_irq(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * This is the first arch callback after mm_init (we can use kmalloc),
72*4882a593Smuzhiyun * so let's finish bus initialization now.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun bcm47xx_bus_setup();
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #ifdef CONFIG_BCM47XX_BCMA
77*4882a593Smuzhiyun if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
78*4882a593Smuzhiyun bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core,
79*4882a593Smuzhiyun BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31);
80*4882a593Smuzhiyun /*
81*4882a593Smuzhiyun * the kernel reads the timer irq from some register and thinks
82*4882a593Smuzhiyun * it's #5, but we offset it by 2 and route to #7
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun cp0_compare_irq = 7;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun #endif
87*4882a593Smuzhiyun mips_cpu_irq_init();
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (cpu_has_vint) {
90*4882a593Smuzhiyun pr_info("Setting up vectored interrupts\n");
91*4882a593Smuzhiyun set_vi_handler(2, bcm47xx_hw2_irqdispatch);
92*4882a593Smuzhiyun set_vi_handler(3, bcm47xx_hw3_irqdispatch);
93*4882a593Smuzhiyun set_vi_handler(4, bcm47xx_hw4_irqdispatch);
94*4882a593Smuzhiyun set_vi_handler(5, bcm47xx_hw5_irqdispatch);
95*4882a593Smuzhiyun set_vi_handler(6, bcm47xx_hw6_irqdispatch);
96*4882a593Smuzhiyun set_vi_handler(7, bcm47xx_hw7_irqdispatch);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun }
99