1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef __ATH25_DEVICES_H
3*4882a593Smuzhiyun #define __ATH25_DEVICES_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun #include <linux/cpu.h>
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun enum ath25_soc_type {
12*4882a593Smuzhiyun /* handled by ar5312.c */
13*4882a593Smuzhiyun ATH25_SOC_AR2312,
14*4882a593Smuzhiyun ATH25_SOC_AR2313,
15*4882a593Smuzhiyun ATH25_SOC_AR5312,
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* handled by ar2315.c */
18*4882a593Smuzhiyun ATH25_SOC_AR2315,
19*4882a593Smuzhiyun ATH25_SOC_AR2316,
20*4882a593Smuzhiyun ATH25_SOC_AR2317,
21*4882a593Smuzhiyun ATH25_SOC_AR2318,
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun ATH25_SOC_UNKNOWN
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun extern enum ath25_soc_type ath25_soc;
27*4882a593Smuzhiyun extern struct ar231x_board_config ath25_board;
28*4882a593Smuzhiyun extern void (*ath25_irq_dispatch)(void);
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun int ath25_find_config(phys_addr_t offset, unsigned long size);
31*4882a593Smuzhiyun void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
32*4882a593Smuzhiyun int ath25_add_wmac(int nr, u32 base, int irq);
33*4882a593Smuzhiyun
is_ar2315(void)34*4882a593Smuzhiyun static inline bool is_ar2315(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return (current_cpu_data.cputype == CPU_4KEC);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
is_ar5312(void)39*4882a593Smuzhiyun static inline bool is_ar5312(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun return !is_ar2315();
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #endif
45