1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
4*4882a593Smuzhiyun * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/dma-mapping.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/mtd/physmap.h>
13*4882a593Smuzhiyun #include <linux/serial.h>
14*4882a593Smuzhiyun #include <linux/serial_8250.h>
15*4882a593Smuzhiyun #include <linux/ioport.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/vlynq.h>
18*4882a593Smuzhiyun #include <linux/leds.h>
19*4882a593Smuzhiyun #include <linux/string.h>
20*4882a593Smuzhiyun #include <linux/etherdevice.h>
21*4882a593Smuzhiyun #include <linux/phy.h>
22*4882a593Smuzhiyun #include <linux/phy_fixed.h>
23*4882a593Smuzhiyun #include <linux/gpio.h>
24*4882a593Smuzhiyun #include <linux/clk.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <asm/addrspace.h>
27*4882a593Smuzhiyun #include <asm/mach-ar7/ar7.h>
28*4882a593Smuzhiyun #include <asm/mach-ar7/prom.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /*****************************************************************************
31*4882a593Smuzhiyun * VLYNQ Bus
32*4882a593Smuzhiyun ****************************************************************************/
33*4882a593Smuzhiyun struct plat_vlynq_data {
34*4882a593Smuzhiyun struct plat_vlynq_ops ops;
35*4882a593Smuzhiyun int gpio_bit;
36*4882a593Smuzhiyun int reset_bit;
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
vlynq_on(struct vlynq_device * dev)39*4882a593Smuzhiyun static int vlynq_on(struct vlynq_device *dev)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun int ret;
42*4882a593Smuzhiyun struct plat_vlynq_data *pdata = dev->dev.platform_data;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun ret = gpio_request(pdata->gpio_bit, "vlynq");
45*4882a593Smuzhiyun if (ret)
46*4882a593Smuzhiyun goto out;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun ar7_device_reset(pdata->reset_bit);
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun ret = ar7_gpio_disable(pdata->gpio_bit);
51*4882a593Smuzhiyun if (ret)
52*4882a593Smuzhiyun goto out_enabled;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun ret = ar7_gpio_enable(pdata->gpio_bit);
55*4882a593Smuzhiyun if (ret)
56*4882a593Smuzhiyun goto out_enabled;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun ret = gpio_direction_output(pdata->gpio_bit, 0);
59*4882a593Smuzhiyun if (ret)
60*4882a593Smuzhiyun goto out_gpio_enabled;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun msleep(50);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun gpio_set_value(pdata->gpio_bit, 1);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun msleep(50);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun return 0;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun out_gpio_enabled:
71*4882a593Smuzhiyun ar7_gpio_disable(pdata->gpio_bit);
72*4882a593Smuzhiyun out_enabled:
73*4882a593Smuzhiyun ar7_device_disable(pdata->reset_bit);
74*4882a593Smuzhiyun gpio_free(pdata->gpio_bit);
75*4882a593Smuzhiyun out:
76*4882a593Smuzhiyun return ret;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
vlynq_off(struct vlynq_device * dev)79*4882a593Smuzhiyun static void vlynq_off(struct vlynq_device *dev)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun struct plat_vlynq_data *pdata = dev->dev.platform_data;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun ar7_gpio_disable(pdata->gpio_bit);
84*4882a593Smuzhiyun gpio_free(pdata->gpio_bit);
85*4882a593Smuzhiyun ar7_device_disable(pdata->reset_bit);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static struct resource vlynq_low_res[] = {
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun .name = "regs",
91*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
92*4882a593Smuzhiyun .start = AR7_REGS_VLYNQ0,
93*4882a593Smuzhiyun .end = AR7_REGS_VLYNQ0 + 0xff,
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun .name = "irq",
97*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
98*4882a593Smuzhiyun .start = 29,
99*4882a593Smuzhiyun .end = 29,
100*4882a593Smuzhiyun },
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .name = "mem",
103*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
104*4882a593Smuzhiyun .start = 0x04000000,
105*4882a593Smuzhiyun .end = 0x04ffffff,
106*4882a593Smuzhiyun },
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun .name = "devirq",
109*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
110*4882a593Smuzhiyun .start = 80,
111*4882a593Smuzhiyun .end = 111,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun static struct resource vlynq_high_res[] = {
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun .name = "regs",
118*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
119*4882a593Smuzhiyun .start = AR7_REGS_VLYNQ1,
120*4882a593Smuzhiyun .end = AR7_REGS_VLYNQ1 + 0xff,
121*4882a593Smuzhiyun },
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun .name = "irq",
124*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
125*4882a593Smuzhiyun .start = 33,
126*4882a593Smuzhiyun .end = 33,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun .name = "mem",
130*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
131*4882a593Smuzhiyun .start = 0x0c000000,
132*4882a593Smuzhiyun .end = 0x0cffffff,
133*4882a593Smuzhiyun },
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun .name = "devirq",
136*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
137*4882a593Smuzhiyun .start = 112,
138*4882a593Smuzhiyun .end = 143,
139*4882a593Smuzhiyun },
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun static struct plat_vlynq_data vlynq_low_data = {
143*4882a593Smuzhiyun .ops = {
144*4882a593Smuzhiyun .on = vlynq_on,
145*4882a593Smuzhiyun .off = vlynq_off,
146*4882a593Smuzhiyun },
147*4882a593Smuzhiyun .reset_bit = 20,
148*4882a593Smuzhiyun .gpio_bit = 18,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static struct plat_vlynq_data vlynq_high_data = {
152*4882a593Smuzhiyun .ops = {
153*4882a593Smuzhiyun .on = vlynq_on,
154*4882a593Smuzhiyun .off = vlynq_off,
155*4882a593Smuzhiyun },
156*4882a593Smuzhiyun .reset_bit = 16,
157*4882a593Smuzhiyun .gpio_bit = 19,
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static struct platform_device vlynq_low = {
161*4882a593Smuzhiyun .id = 0,
162*4882a593Smuzhiyun .name = "vlynq",
163*4882a593Smuzhiyun .dev = {
164*4882a593Smuzhiyun .platform_data = &vlynq_low_data,
165*4882a593Smuzhiyun },
166*4882a593Smuzhiyun .resource = vlynq_low_res,
167*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(vlynq_low_res),
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun static struct platform_device vlynq_high = {
171*4882a593Smuzhiyun .id = 1,
172*4882a593Smuzhiyun .name = "vlynq",
173*4882a593Smuzhiyun .dev = {
174*4882a593Smuzhiyun .platform_data = &vlynq_high_data,
175*4882a593Smuzhiyun },
176*4882a593Smuzhiyun .resource = vlynq_high_res,
177*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(vlynq_high_res),
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun /*****************************************************************************
181*4882a593Smuzhiyun * Flash
182*4882a593Smuzhiyun ****************************************************************************/
183*4882a593Smuzhiyun static struct resource physmap_flash_resource = {
184*4882a593Smuzhiyun .name = "mem",
185*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
186*4882a593Smuzhiyun .start = 0x10000000,
187*4882a593Smuzhiyun .end = 0x107fffff,
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static const char *ar7_probe_types[] = { "ar7part", NULL };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static struct physmap_flash_data physmap_flash_data = {
193*4882a593Smuzhiyun .width = 2,
194*4882a593Smuzhiyun .part_probe_types = ar7_probe_types,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun static struct platform_device physmap_flash = {
198*4882a593Smuzhiyun .name = "physmap-flash",
199*4882a593Smuzhiyun .dev = {
200*4882a593Smuzhiyun .platform_data = &physmap_flash_data,
201*4882a593Smuzhiyun },
202*4882a593Smuzhiyun .resource = &physmap_flash_resource,
203*4882a593Smuzhiyun .num_resources = 1,
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /*****************************************************************************
207*4882a593Smuzhiyun * Ethernet
208*4882a593Smuzhiyun ****************************************************************************/
209*4882a593Smuzhiyun static struct resource cpmac_low_res[] = {
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun .name = "regs",
212*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
213*4882a593Smuzhiyun .start = AR7_REGS_MAC0,
214*4882a593Smuzhiyun .end = AR7_REGS_MAC0 + 0x7ff,
215*4882a593Smuzhiyun },
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun .name = "irq",
218*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
219*4882a593Smuzhiyun .start = 27,
220*4882a593Smuzhiyun .end = 27,
221*4882a593Smuzhiyun },
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun static struct resource cpmac_high_res[] = {
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun .name = "regs",
227*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
228*4882a593Smuzhiyun .start = AR7_REGS_MAC1,
229*4882a593Smuzhiyun .end = AR7_REGS_MAC1 + 0x7ff,
230*4882a593Smuzhiyun },
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun .name = "irq",
233*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
234*4882a593Smuzhiyun .start = 41,
235*4882a593Smuzhiyun .end = 41,
236*4882a593Smuzhiyun },
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static struct fixed_phy_status fixed_phy_status __initdata = {
240*4882a593Smuzhiyun .link = 1,
241*4882a593Smuzhiyun .speed = 100,
242*4882a593Smuzhiyun .duplex = 1,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static struct plat_cpmac_data cpmac_low_data = {
246*4882a593Smuzhiyun .reset_bit = 17,
247*4882a593Smuzhiyun .power_bit = 20,
248*4882a593Smuzhiyun .phy_mask = 0x80000000,
249*4882a593Smuzhiyun };
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun static struct plat_cpmac_data cpmac_high_data = {
252*4882a593Smuzhiyun .reset_bit = 21,
253*4882a593Smuzhiyun .power_bit = 22,
254*4882a593Smuzhiyun .phy_mask = 0x7fffffff,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static u64 cpmac_dma_mask = DMA_BIT_MASK(32);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static struct platform_device cpmac_low = {
260*4882a593Smuzhiyun .id = 0,
261*4882a593Smuzhiyun .name = "cpmac",
262*4882a593Smuzhiyun .dev = {
263*4882a593Smuzhiyun .dma_mask = &cpmac_dma_mask,
264*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
265*4882a593Smuzhiyun .platform_data = &cpmac_low_data,
266*4882a593Smuzhiyun },
267*4882a593Smuzhiyun .resource = cpmac_low_res,
268*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(cpmac_low_res),
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static struct platform_device cpmac_high = {
272*4882a593Smuzhiyun .id = 1,
273*4882a593Smuzhiyun .name = "cpmac",
274*4882a593Smuzhiyun .dev = {
275*4882a593Smuzhiyun .dma_mask = &cpmac_dma_mask,
276*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
277*4882a593Smuzhiyun .platform_data = &cpmac_high_data,
278*4882a593Smuzhiyun },
279*4882a593Smuzhiyun .resource = cpmac_high_res,
280*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(cpmac_high_res),
281*4882a593Smuzhiyun };
282*4882a593Smuzhiyun
cpmac_get_mac(int instance,unsigned char * dev_addr)283*4882a593Smuzhiyun static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun char name[5], *mac;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun sprintf(name, "mac%c", 'a' + instance);
288*4882a593Smuzhiyun mac = prom_getenv(name);
289*4882a593Smuzhiyun if (!mac && instance) {
290*4882a593Smuzhiyun sprintf(name, "mac%c", 'a');
291*4882a593Smuzhiyun mac = prom_getenv(name);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun if (mac) {
295*4882a593Smuzhiyun if (!mac_pton(mac, dev_addr)) {
296*4882a593Smuzhiyun pr_warn("cannot parse mac address, using random address\n");
297*4882a593Smuzhiyun eth_random_addr(dev_addr);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun } else
300*4882a593Smuzhiyun eth_random_addr(dev_addr);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /*****************************************************************************
304*4882a593Smuzhiyun * USB
305*4882a593Smuzhiyun ****************************************************************************/
306*4882a593Smuzhiyun static struct resource usb_res[] = {
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun .name = "regs",
309*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
310*4882a593Smuzhiyun .start = AR7_REGS_USB,
311*4882a593Smuzhiyun .end = AR7_REGS_USB + 0xff,
312*4882a593Smuzhiyun },
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun .name = "irq",
315*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
316*4882a593Smuzhiyun .start = 32,
317*4882a593Smuzhiyun .end = 32,
318*4882a593Smuzhiyun },
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun .name = "mem",
321*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
322*4882a593Smuzhiyun .start = 0x03400000,
323*4882a593Smuzhiyun .end = 0x03401fff,
324*4882a593Smuzhiyun },
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun static struct platform_device ar7_udc = {
328*4882a593Smuzhiyun .name = "ar7_udc",
329*4882a593Smuzhiyun .resource = usb_res,
330*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(usb_res),
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun /*****************************************************************************
334*4882a593Smuzhiyun * LEDs
335*4882a593Smuzhiyun ****************************************************************************/
336*4882a593Smuzhiyun static const struct gpio_led default_leds[] = {
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun .name = "status",
339*4882a593Smuzhiyun .gpio = 8,
340*4882a593Smuzhiyun .active_low = 1,
341*4882a593Smuzhiyun },
342*4882a593Smuzhiyun };
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static const struct gpio_led titan_leds[] = {
345*4882a593Smuzhiyun { .name = "status", .gpio = 8, .active_low = 1, },
346*4882a593Smuzhiyun { .name = "wifi", .gpio = 13, .active_low = 1, },
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun static const struct gpio_led dsl502t_leds[] = {
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun .name = "status",
352*4882a593Smuzhiyun .gpio = 9,
353*4882a593Smuzhiyun .active_low = 1,
354*4882a593Smuzhiyun },
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun .name = "ethernet",
357*4882a593Smuzhiyun .gpio = 7,
358*4882a593Smuzhiyun .active_low = 1,
359*4882a593Smuzhiyun },
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun .name = "usb",
362*4882a593Smuzhiyun .gpio = 12,
363*4882a593Smuzhiyun .active_low = 1,
364*4882a593Smuzhiyun },
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun static const struct gpio_led dg834g_leds[] = {
368*4882a593Smuzhiyun {
369*4882a593Smuzhiyun .name = "ppp",
370*4882a593Smuzhiyun .gpio = 6,
371*4882a593Smuzhiyun .active_low = 1,
372*4882a593Smuzhiyun },
373*4882a593Smuzhiyun {
374*4882a593Smuzhiyun .name = "status",
375*4882a593Smuzhiyun .gpio = 7,
376*4882a593Smuzhiyun .active_low = 1,
377*4882a593Smuzhiyun },
378*4882a593Smuzhiyun {
379*4882a593Smuzhiyun .name = "adsl",
380*4882a593Smuzhiyun .gpio = 8,
381*4882a593Smuzhiyun .active_low = 1,
382*4882a593Smuzhiyun },
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun .name = "wifi",
385*4882a593Smuzhiyun .gpio = 12,
386*4882a593Smuzhiyun .active_low = 1,
387*4882a593Smuzhiyun },
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun .name = "power",
390*4882a593Smuzhiyun .gpio = 14,
391*4882a593Smuzhiyun .active_low = 1,
392*4882a593Smuzhiyun .default_trigger = "default-on",
393*4882a593Smuzhiyun },
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun static const struct gpio_led fb_sl_leds[] = {
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun .name = "1",
399*4882a593Smuzhiyun .gpio = 7,
400*4882a593Smuzhiyun },
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun .name = "2",
403*4882a593Smuzhiyun .gpio = 13,
404*4882a593Smuzhiyun .active_low = 1,
405*4882a593Smuzhiyun },
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun .name = "3",
408*4882a593Smuzhiyun .gpio = 10,
409*4882a593Smuzhiyun .active_low = 1,
410*4882a593Smuzhiyun },
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun .name = "4",
413*4882a593Smuzhiyun .gpio = 12,
414*4882a593Smuzhiyun .active_low = 1,
415*4882a593Smuzhiyun },
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun .name = "5",
418*4882a593Smuzhiyun .gpio = 9,
419*4882a593Smuzhiyun .active_low = 1,
420*4882a593Smuzhiyun },
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun static const struct gpio_led fb_fon_leds[] = {
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun .name = "1",
426*4882a593Smuzhiyun .gpio = 8,
427*4882a593Smuzhiyun },
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun .name = "2",
430*4882a593Smuzhiyun .gpio = 3,
431*4882a593Smuzhiyun .active_low = 1,
432*4882a593Smuzhiyun },
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun .name = "3",
435*4882a593Smuzhiyun .gpio = 5,
436*4882a593Smuzhiyun },
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun .name = "4",
439*4882a593Smuzhiyun .gpio = 4,
440*4882a593Smuzhiyun .active_low = 1,
441*4882a593Smuzhiyun },
442*4882a593Smuzhiyun {
443*4882a593Smuzhiyun .name = "5",
444*4882a593Smuzhiyun .gpio = 11,
445*4882a593Smuzhiyun .active_low = 1,
446*4882a593Smuzhiyun },
447*4882a593Smuzhiyun };
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun static const struct gpio_led gt701_leds[] = {
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun .name = "inet:green",
452*4882a593Smuzhiyun .gpio = 13,
453*4882a593Smuzhiyun .active_low = 1,
454*4882a593Smuzhiyun },
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun .name = "usb",
457*4882a593Smuzhiyun .gpio = 12,
458*4882a593Smuzhiyun .active_low = 1,
459*4882a593Smuzhiyun },
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun .name = "inet:red",
462*4882a593Smuzhiyun .gpio = 9,
463*4882a593Smuzhiyun .active_low = 1,
464*4882a593Smuzhiyun },
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun .name = "power:red",
467*4882a593Smuzhiyun .gpio = 7,
468*4882a593Smuzhiyun .active_low = 1,
469*4882a593Smuzhiyun },
470*4882a593Smuzhiyun {
471*4882a593Smuzhiyun .name = "power:green",
472*4882a593Smuzhiyun .gpio = 8,
473*4882a593Smuzhiyun .active_low = 1,
474*4882a593Smuzhiyun .default_trigger = "default-on",
475*4882a593Smuzhiyun },
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun .name = "ethernet",
478*4882a593Smuzhiyun .gpio = 10,
479*4882a593Smuzhiyun .active_low = 1,
480*4882a593Smuzhiyun },
481*4882a593Smuzhiyun };
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun static struct gpio_led_platform_data ar7_led_data;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun static struct platform_device ar7_gpio_leds = {
486*4882a593Smuzhiyun .name = "leds-gpio",
487*4882a593Smuzhiyun .dev = {
488*4882a593Smuzhiyun .platform_data = &ar7_led_data,
489*4882a593Smuzhiyun }
490*4882a593Smuzhiyun };
491*4882a593Smuzhiyun
detect_leds(void)492*4882a593Smuzhiyun static void __init detect_leds(void)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun char *prid, *usb_prod;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun /* Default LEDs */
497*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
498*4882a593Smuzhiyun ar7_led_data.leds = default_leds;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /* FIXME: the whole thing is unreliable */
501*4882a593Smuzhiyun prid = prom_getenv("ProductID");
502*4882a593Smuzhiyun usb_prod = prom_getenv("usb_prod");
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /* If we can't get the product id from PROM, use the default LEDs */
505*4882a593Smuzhiyun if (!prid)
506*4882a593Smuzhiyun return;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun if (strstr(prid, "Fritz_Box_FON")) {
509*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds);
510*4882a593Smuzhiyun ar7_led_data.leds = fb_fon_leds;
511*4882a593Smuzhiyun } else if (strstr(prid, "Fritz_Box_")) {
512*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds);
513*4882a593Smuzhiyun ar7_led_data.leds = fb_sl_leds;
514*4882a593Smuzhiyun } else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB"))
515*4882a593Smuzhiyun && usb_prod != NULL && strstr(usb_prod, "DSL-502T")) {
516*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds);
517*4882a593Smuzhiyun ar7_led_data.leds = dsl502t_leds;
518*4882a593Smuzhiyun } else if (strstr(prid, "DG834")) {
519*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
520*4882a593Smuzhiyun ar7_led_data.leds = dg834g_leds;
521*4882a593Smuzhiyun } else if (strstr(prid, "CYWM") || strstr(prid, "CYWL")) {
522*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(titan_leds);
523*4882a593Smuzhiyun ar7_led_data.leds = titan_leds;
524*4882a593Smuzhiyun } else if (strstr(prid, "GT701")) {
525*4882a593Smuzhiyun ar7_led_data.num_leds = ARRAY_SIZE(gt701_leds);
526*4882a593Smuzhiyun ar7_led_data.leds = gt701_leds;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun /*****************************************************************************
531*4882a593Smuzhiyun * Watchdog
532*4882a593Smuzhiyun ****************************************************************************/
533*4882a593Smuzhiyun static struct resource ar7_wdt_res = {
534*4882a593Smuzhiyun .name = "regs",
535*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
536*4882a593Smuzhiyun .start = -1, /* Filled at runtime */
537*4882a593Smuzhiyun .end = -1, /* Filled at runtime */
538*4882a593Smuzhiyun };
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun static struct platform_device ar7_wdt = {
541*4882a593Smuzhiyun .name = "ar7_wdt",
542*4882a593Smuzhiyun .resource = &ar7_wdt_res,
543*4882a593Smuzhiyun .num_resources = 1,
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun /*****************************************************************************
547*4882a593Smuzhiyun * Init
548*4882a593Smuzhiyun ****************************************************************************/
ar7_register_uarts(void)549*4882a593Smuzhiyun static int __init ar7_register_uarts(void)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun #ifdef CONFIG_SERIAL_8250
552*4882a593Smuzhiyun static struct uart_port uart_port __initdata;
553*4882a593Smuzhiyun struct clk *bus_clk;
554*4882a593Smuzhiyun int res;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun memset(&uart_port, 0, sizeof(struct uart_port));
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun bus_clk = clk_get(NULL, "bus");
559*4882a593Smuzhiyun if (IS_ERR(bus_clk))
560*4882a593Smuzhiyun panic("unable to get bus clk");
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun uart_port.type = PORT_AR7;
563*4882a593Smuzhiyun uart_port.uartclk = clk_get_rate(bus_clk) / 2;
564*4882a593Smuzhiyun uart_port.iotype = UPIO_MEM32;
565*4882a593Smuzhiyun uart_port.flags = UPF_FIXED_TYPE | UPF_BOOT_AUTOCONF;
566*4882a593Smuzhiyun uart_port.regshift = 2;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun uart_port.line = 0;
569*4882a593Smuzhiyun uart_port.irq = AR7_IRQ_UART0;
570*4882a593Smuzhiyun uart_port.mapbase = AR7_REGS_UART0;
571*4882a593Smuzhiyun uart_port.membase = ioremap(uart_port.mapbase, 256);
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun res = early_serial_setup(&uart_port);
574*4882a593Smuzhiyun if (res)
575*4882a593Smuzhiyun return res;
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun /* Only TNETD73xx have a second serial port */
578*4882a593Smuzhiyun if (ar7_has_second_uart()) {
579*4882a593Smuzhiyun uart_port.line = 1;
580*4882a593Smuzhiyun uart_port.irq = AR7_IRQ_UART1;
581*4882a593Smuzhiyun uart_port.mapbase = UR8_REGS_UART1;
582*4882a593Smuzhiyun uart_port.membase = ioremap(uart_port.mapbase, 256);
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun res = early_serial_setup(&uart_port);
585*4882a593Smuzhiyun if (res)
586*4882a593Smuzhiyun return res;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun #endif
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun return 0;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun
titan_fixup_devices(void)593*4882a593Smuzhiyun static void __init titan_fixup_devices(void)
594*4882a593Smuzhiyun {
595*4882a593Smuzhiyun /* Set vlynq0 data */
596*4882a593Smuzhiyun vlynq_low_data.reset_bit = 15;
597*4882a593Smuzhiyun vlynq_low_data.gpio_bit = 14;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* Set vlynq1 data */
600*4882a593Smuzhiyun vlynq_high_data.reset_bit = 16;
601*4882a593Smuzhiyun vlynq_high_data.gpio_bit = 7;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun /* Set vlynq0 resources */
604*4882a593Smuzhiyun vlynq_low_res[0].start = TITAN_REGS_VLYNQ0;
605*4882a593Smuzhiyun vlynq_low_res[0].end = TITAN_REGS_VLYNQ0 + 0xff;
606*4882a593Smuzhiyun vlynq_low_res[1].start = 33;
607*4882a593Smuzhiyun vlynq_low_res[1].end = 33;
608*4882a593Smuzhiyun vlynq_low_res[2].start = 0x0c000000;
609*4882a593Smuzhiyun vlynq_low_res[2].end = 0x0fffffff;
610*4882a593Smuzhiyun vlynq_low_res[3].start = 80;
611*4882a593Smuzhiyun vlynq_low_res[3].end = 111;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun /* Set vlynq1 resources */
614*4882a593Smuzhiyun vlynq_high_res[0].start = TITAN_REGS_VLYNQ1;
615*4882a593Smuzhiyun vlynq_high_res[0].end = TITAN_REGS_VLYNQ1 + 0xff;
616*4882a593Smuzhiyun vlynq_high_res[1].start = 34;
617*4882a593Smuzhiyun vlynq_high_res[1].end = 34;
618*4882a593Smuzhiyun vlynq_high_res[2].start = 0x40000000;
619*4882a593Smuzhiyun vlynq_high_res[2].end = 0x43ffffff;
620*4882a593Smuzhiyun vlynq_high_res[3].start = 112;
621*4882a593Smuzhiyun vlynq_high_res[3].end = 143;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun /* Set cpmac0 data */
624*4882a593Smuzhiyun cpmac_low_data.phy_mask = 0x40000000;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun /* Set cpmac1 data */
627*4882a593Smuzhiyun cpmac_high_data.phy_mask = 0x80000000;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun /* Set cpmac0 resources */
630*4882a593Smuzhiyun cpmac_low_res[0].start = TITAN_REGS_MAC0;
631*4882a593Smuzhiyun cpmac_low_res[0].end = TITAN_REGS_MAC0 + 0x7ff;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun /* Set cpmac1 resources */
634*4882a593Smuzhiyun cpmac_high_res[0].start = TITAN_REGS_MAC1;
635*4882a593Smuzhiyun cpmac_high_res[0].end = TITAN_REGS_MAC1 + 0x7ff;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
ar7_register_devices(void)638*4882a593Smuzhiyun static int __init ar7_register_devices(void)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun void __iomem *bootcr;
641*4882a593Smuzhiyun u32 val;
642*4882a593Smuzhiyun int res;
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun res = ar7_gpio_init();
645*4882a593Smuzhiyun if (res)
646*4882a593Smuzhiyun pr_warn("unable to register gpios: %d\n", res);
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun res = ar7_register_uarts();
649*4882a593Smuzhiyun if (res)
650*4882a593Smuzhiyun pr_err("unable to setup uart(s): %d\n", res);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun res = platform_device_register(&physmap_flash);
653*4882a593Smuzhiyun if (res)
654*4882a593Smuzhiyun pr_warn("unable to register physmap-flash: %d\n", res);
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun if (ar7_is_titan())
657*4882a593Smuzhiyun titan_fixup_devices();
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun ar7_device_disable(vlynq_low_data.reset_bit);
660*4882a593Smuzhiyun res = platform_device_register(&vlynq_low);
661*4882a593Smuzhiyun if (res)
662*4882a593Smuzhiyun pr_warn("unable to register vlynq-low: %d\n", res);
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun if (ar7_has_high_vlynq()) {
665*4882a593Smuzhiyun ar7_device_disable(vlynq_high_data.reset_bit);
666*4882a593Smuzhiyun res = platform_device_register(&vlynq_high);
667*4882a593Smuzhiyun if (res)
668*4882a593Smuzhiyun pr_warn("unable to register vlynq-high: %d\n", res);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun if (ar7_has_high_cpmac()) {
672*4882a593Smuzhiyun res = fixed_phy_add(PHY_POLL, cpmac_high.id,
673*4882a593Smuzhiyun &fixed_phy_status);
674*4882a593Smuzhiyun if (!res) {
675*4882a593Smuzhiyun cpmac_get_mac(1, cpmac_high_data.dev_addr);
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun res = platform_device_register(&cpmac_high);
678*4882a593Smuzhiyun if (res)
679*4882a593Smuzhiyun pr_warn("unable to register cpmac-high: %d\n",
680*4882a593Smuzhiyun res);
681*4882a593Smuzhiyun } else
682*4882a593Smuzhiyun pr_warn("unable to add cpmac-high phy: %d\n", res);
683*4882a593Smuzhiyun } else
684*4882a593Smuzhiyun cpmac_low_data.phy_mask = 0xffffffff;
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
687*4882a593Smuzhiyun if (!res) {
688*4882a593Smuzhiyun cpmac_get_mac(0, cpmac_low_data.dev_addr);
689*4882a593Smuzhiyun res = platform_device_register(&cpmac_low);
690*4882a593Smuzhiyun if (res)
691*4882a593Smuzhiyun pr_warn("unable to register cpmac-low: %d\n", res);
692*4882a593Smuzhiyun } else
693*4882a593Smuzhiyun pr_warn("unable to add cpmac-low phy: %d\n", res);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun detect_leds();
696*4882a593Smuzhiyun res = platform_device_register(&ar7_gpio_leds);
697*4882a593Smuzhiyun if (res)
698*4882a593Smuzhiyun pr_warn("unable to register leds: %d\n", res);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun res = platform_device_register(&ar7_udc);
701*4882a593Smuzhiyun if (res)
702*4882a593Smuzhiyun pr_warn("unable to register usb slave: %d\n", res);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun /* Register watchdog only if enabled in hardware */
705*4882a593Smuzhiyun bootcr = ioremap(AR7_REGS_DCL, 4);
706*4882a593Smuzhiyun val = readl(bootcr);
707*4882a593Smuzhiyun iounmap(bootcr);
708*4882a593Smuzhiyun if (val & AR7_WDT_HW_ENA) {
709*4882a593Smuzhiyun if (ar7_has_high_vlynq())
710*4882a593Smuzhiyun ar7_wdt_res.start = UR8_REGS_WDT;
711*4882a593Smuzhiyun else
712*4882a593Smuzhiyun ar7_wdt_res.start = AR7_REGS_WDT;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
715*4882a593Smuzhiyun res = platform_device_register(&ar7_wdt);
716*4882a593Smuzhiyun if (res)
717*4882a593Smuzhiyun pr_warn("unable to register watchdog: %d\n", res);
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun
720*4882a593Smuzhiyun return 0;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun device_initcall(ar7_register_devices);
723