1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2000, 2007-2008 MontaVista Software Inc.
3*4882a593Smuzhiyun * Author: MontaVista Software, Inc. <source@mvista.com
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
8*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the
9*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your
10*4882a593Smuzhiyun * option) any later version.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along
24*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc.,
25*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA.
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <linux/init.h>
29*4882a593Smuzhiyun #include <linux/ioport.h>
30*4882a593Smuzhiyun #include <linux/mm.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <asm/dma-coherence.h>
33*4882a593Smuzhiyun #include <asm/mipsregs.h>
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <au1000.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun extern void __init board_setup(void);
38*4882a593Smuzhiyun extern void __init alchemy_set_lpj(void);
39*4882a593Smuzhiyun
plat_mem_setup(void)40*4882a593Smuzhiyun void __init plat_mem_setup(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun alchemy_set_lpj();
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun if (au1xxx_cpu_needs_config_od())
45*4882a593Smuzhiyun /* Various early Au1xx0 errata corrected by this */
46*4882a593Smuzhiyun set_c0_config(1 << 19); /* Set Config[OD] */
47*4882a593Smuzhiyun else
48*4882a593Smuzhiyun /* Clear to obtain best system bus performance */
49*4882a593Smuzhiyun clear_c0_config(1 << 19); /* Clear Config[OD] */
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun hw_coherentio = 0;
52*4882a593Smuzhiyun coherentio = IO_COHERENCE_ENABLED;
53*4882a593Smuzhiyun switch (alchemy_get_cputype()) {
54*4882a593Smuzhiyun case ALCHEMY_CPU_AU1000:
55*4882a593Smuzhiyun case ALCHEMY_CPU_AU1500:
56*4882a593Smuzhiyun case ALCHEMY_CPU_AU1100:
57*4882a593Smuzhiyun coherentio = IO_COHERENCE_DISABLED;
58*4882a593Smuzhiyun break;
59*4882a593Smuzhiyun case ALCHEMY_CPU_AU1200:
60*4882a593Smuzhiyun /* Au1200 AB USB does not support coherent memory */
61*4882a593Smuzhiyun if (0 == (read_c0_prid() & PRID_REV_MASK))
62*4882a593Smuzhiyun coherentio = IO_COHERENCE_DISABLED;
63*4882a593Smuzhiyun break;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun board_setup(); /* board specific setup */
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* IO/MEM resources. */
69*4882a593Smuzhiyun set_io_port_base(0);
70*4882a593Smuzhiyun ioport_resource.start = IOPORT_RESOURCE_START;
71*4882a593Smuzhiyun ioport_resource.end = IOPORT_RESOURCE_END;
72*4882a593Smuzhiyun iomem_resource.start = IOMEM_RESOURCE_START;
73*4882a593Smuzhiyun iomem_resource.end = IOMEM_RESOURCE_END;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
77*4882a593Smuzhiyun /* This routine should be valid for all Au1x based boards */
fixup_bigphys_addr(phys_addr_t phys_addr,phys_addr_t size)78*4882a593Smuzhiyun phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun unsigned long start = ALCHEMY_PCI_MEMWIN_START;
81*4882a593Smuzhiyun unsigned long end = ALCHEMY_PCI_MEMWIN_END;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Don't fixup 36-bit addresses */
84*4882a593Smuzhiyun if ((phys_addr >> 32) != 0)
85*4882a593Smuzhiyun return phys_addr;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Check for PCI memory window */
88*4882a593Smuzhiyun if (phys_addr >= start && (phys_addr + size - 1) <= end)
89*4882a593Smuzhiyun return (phys_addr_t)(AU1500_PCI_MEM_PHYS_ADDR + phys_addr);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* default nop */
92*4882a593Smuzhiyun return phys_addr;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
io_remap_pfn_range(struct vm_area_struct * vma,unsigned long vaddr,unsigned long pfn,unsigned long size,pgprot_t prot)95*4882a593Smuzhiyun int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
96*4882a593Smuzhiyun unsigned long pfn, unsigned long size, pgprot_t prot)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun EXPORT_SYMBOL(io_remap_pfn_range);
103*4882a593Smuzhiyun #endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
104