1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * BRIEF MODULE DESCRIPTION
3*4882a593Smuzhiyun * Au1xx0 Power Management routines.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2001, 2008 MontaVista Software Inc.
6*4882a593Smuzhiyun * Author: MontaVista Software, Inc. <source@mvista.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Some of the routines are right out of init/main.c, whose
9*4882a593Smuzhiyun * copyrights apply here.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
12*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the
13*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your
14*4882a593Smuzhiyun * option) any later version.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19*4882a593Smuzhiyun * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21*4882a593Smuzhiyun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22*4882a593Smuzhiyun * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23*4882a593Smuzhiyun * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25*4882a593Smuzhiyun * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along
28*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc.,
29*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA.
30*4882a593Smuzhiyun */
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <linux/pm.h>
33*4882a593Smuzhiyun #include <linux/sysctl.h>
34*4882a593Smuzhiyun #include <linux/jiffies.h>
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/uaccess.h>
37*4882a593Smuzhiyun #include <asm/mach-au1x00/au1000.h>
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * We need to save/restore a bunch of core registers that are
41*4882a593Smuzhiyun * either volatile or reset to some state across a processor sleep.
42*4882a593Smuzhiyun * If reading a register doesn't provide a proper result for a
43*4882a593Smuzhiyun * later restore, we have to provide a function for loading that
44*4882a593Smuzhiyun * register and save a copy.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun * We only have to save/restore registers that aren't otherwise
47*4882a593Smuzhiyun * done as part of a driver pm_* function.
48*4882a593Smuzhiyun */
49*4882a593Smuzhiyun static unsigned int sleep_sys_clocks[5];
50*4882a593Smuzhiyun static unsigned int sleep_sys_pinfunc;
51*4882a593Smuzhiyun static unsigned int sleep_static_memctlr[4][3];
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun
save_core_regs(void)54*4882a593Smuzhiyun static void save_core_regs(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun /* Clocks and PLLs. */
57*4882a593Smuzhiyun sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0);
58*4882a593Smuzhiyun sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1);
59*4882a593Smuzhiyun sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC);
60*4882a593Smuzhiyun sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL);
61*4882a593Smuzhiyun sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* pin mux config */
64*4882a593Smuzhiyun sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Save the static memory controller configuration. */
67*4882a593Smuzhiyun sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
68*4882a593Smuzhiyun sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
69*4882a593Smuzhiyun sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
70*4882a593Smuzhiyun sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
71*4882a593Smuzhiyun sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
72*4882a593Smuzhiyun sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
73*4882a593Smuzhiyun sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
74*4882a593Smuzhiyun sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
75*4882a593Smuzhiyun sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
76*4882a593Smuzhiyun sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
77*4882a593Smuzhiyun sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
78*4882a593Smuzhiyun sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
restore_core_regs(void)81*4882a593Smuzhiyun static void restore_core_regs(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun /* restore clock configuration. Writing CPUPLL last will
84*4882a593Smuzhiyun * stall a bit and stabilize other clocks (unless this is
85*4882a593Smuzhiyun * one of those Au1000 with a write-only PLL, where we dont
86*4882a593Smuzhiyun * have a valid value)
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0);
89*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1);
90*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC);
91*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL);
92*4882a593Smuzhiyun if (!au1xxx_cpu_has_pll_wo())
93*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun /* Restore the static memory controller configuration. */
98*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
99*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
100*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
101*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
102*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
103*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
104*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
105*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
106*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
107*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
108*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
109*4882a593Smuzhiyun alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
au_sleep(void)112*4882a593Smuzhiyun void au_sleep(void)
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun save_core_regs();
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun switch (alchemy_get_cputype()) {
117*4882a593Smuzhiyun case ALCHEMY_CPU_AU1000:
118*4882a593Smuzhiyun case ALCHEMY_CPU_AU1500:
119*4882a593Smuzhiyun case ALCHEMY_CPU_AU1100:
120*4882a593Smuzhiyun alchemy_sleep_au1000();
121*4882a593Smuzhiyun break;
122*4882a593Smuzhiyun case ALCHEMY_CPU_AU1550:
123*4882a593Smuzhiyun case ALCHEMY_CPU_AU1200:
124*4882a593Smuzhiyun alchemy_sleep_au1550();
125*4882a593Smuzhiyun break;
126*4882a593Smuzhiyun case ALCHEMY_CPU_AU1300:
127*4882a593Smuzhiyun alchemy_sleep_au1300();
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun restore_core_regs();
132*4882a593Smuzhiyun }
133