1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Microblaze support for cache consistent memory. 4*4882a593Smuzhiyun * Copyright (C) 2010 Michal Simek <monstr@monstr.eu> 5*4882a593Smuzhiyun * Copyright (C) 2010 PetaLogix 6*4882a593Smuzhiyun * Copyright (C) 2005 John Williams <jwilliams@itee.uq.edu.au> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/kernel.h> 10*4882a593Smuzhiyun #include <linux/string.h> 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun #include <linux/mm.h> 13*4882a593Smuzhiyun #include <linux/init.h> 14*4882a593Smuzhiyun #include <linux/dma-map-ops.h> 15*4882a593Smuzhiyun #include <asm/cpuinfo.h> 16*4882a593Smuzhiyun #include <asm/cacheflush.h> 17*4882a593Smuzhiyun arch_dma_prep_coherent(struct page * page,size_t size)18*4882a593Smuzhiyunvoid arch_dma_prep_coherent(struct page *page, size_t size) 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun phys_addr_t paddr = page_to_phys(page); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun flush_dcache_range(paddr, paddr + size); 23*4882a593Smuzhiyun } 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifndef CONFIG_MMU 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * Consistent memory allocators. Used for DMA devices that want to share 28*4882a593Smuzhiyun * uncached memory with the processor core. My crufty no-MMU approach is 29*4882a593Smuzhiyun * simple. In the HW platform we can optionally mirror the DDR up above the 30*4882a593Smuzhiyun * processor cacheable region. So, memory accessed in this mirror region will 31*4882a593Smuzhiyun * not be cached. It's alloced from the same pool as normal memory, but the 32*4882a593Smuzhiyun * handle we return is shifted up into the uncached region. This will no doubt 33*4882a593Smuzhiyun * cause big problems if memory allocated here is not also freed properly. -- JW 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * I have to use dcache values because I can't relate on ram size: 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun #ifdef CONFIG_XILINX_UNCACHED_SHADOW 38*4882a593Smuzhiyun #define UNCACHED_SHADOW_MASK (cpuinfo.dcache_high - cpuinfo.dcache_base + 1) 39*4882a593Smuzhiyun #else 40*4882a593Smuzhiyun #define UNCACHED_SHADOW_MASK 0 41*4882a593Smuzhiyun #endif /* CONFIG_XILINX_UNCACHED_SHADOW */ 42*4882a593Smuzhiyun arch_dma_set_uncached(void * ptr,size_t size)43*4882a593Smuzhiyunvoid *arch_dma_set_uncached(void *ptr, size_t size) 44*4882a593Smuzhiyun { 45*4882a593Smuzhiyun unsigned long addr = (unsigned long)ptr; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun addr |= UNCACHED_SHADOW_MASK; 48*4882a593Smuzhiyun if (addr > cpuinfo.dcache_base && addr < cpuinfo.dcache_high) 49*4882a593Smuzhiyun pr_warn("ERROR: Your cache coherent area is CACHED!!!\n"); 50*4882a593Smuzhiyun return (void *)addr; 51*4882a593Smuzhiyun } 52*4882a593Smuzhiyun #endif /* CONFIG_MMU */ 53