1*4882a593Smuzhiyun/* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun#include <linux/linkage.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun/* 5*4882a593Smuzhiyun* modulo operation for 32 bit integers. 6*4882a593Smuzhiyun* Input : op1 in Reg r5 7*4882a593Smuzhiyun* op2 in Reg r6 8*4882a593Smuzhiyun* Output: op1 mod op2 in Reg r3 9*4882a593Smuzhiyun*/ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun .text 12*4882a593Smuzhiyun .globl __modsi3 13*4882a593Smuzhiyun .type __modsi3, @function 14*4882a593Smuzhiyun .ent __modsi3 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun__modsi3: 17*4882a593Smuzhiyun .frame r1, 0, r15 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun addik r1, r1, -16 20*4882a593Smuzhiyun swi r28, r1, 0 21*4882a593Smuzhiyun swi r29, r1, 4 22*4882a593Smuzhiyun swi r30, r1, 8 23*4882a593Smuzhiyun swi r31, r1, 12 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun beqi r6, div_by_zero /* div_by_zero division error */ 26*4882a593Smuzhiyun beqi r5, result_is_zero /* result is zero */ 27*4882a593Smuzhiyun bgeid r5, r5_pos 28*4882a593Smuzhiyun /* get the sign of the result [ depends only on the first arg] */ 29*4882a593Smuzhiyun add r28, r5, r0 30*4882a593Smuzhiyun rsubi r5, r5, 0 /* make r5 positive */ 31*4882a593Smuzhiyunr5_pos: 32*4882a593Smuzhiyun bgei r6, r6_pos 33*4882a593Smuzhiyun rsubi r6, r6, 0 /* make r6 positive */ 34*4882a593Smuzhiyunr6_pos: 35*4882a593Smuzhiyun addik r3, r0, 0 /* clear mod */ 36*4882a593Smuzhiyun addik r30, r0, 0 /* clear div */ 37*4882a593Smuzhiyun addik r29, r0, 32 /* initialize the loop count */ 38*4882a593Smuzhiyun/* first part try to find the first '1' in the r5 */ 39*4882a593Smuzhiyundiv1: 40*4882a593Smuzhiyun add r5, r5, r5 /* left shift logical r5 */ 41*4882a593Smuzhiyun bgeid r5, div1 42*4882a593Smuzhiyun addik r29, r29, -1 43*4882a593Smuzhiyundiv2: 44*4882a593Smuzhiyun /* left shift logical r5 get the '1' into the carry */ 45*4882a593Smuzhiyun add r5, r5, r5 46*4882a593Smuzhiyun addc r3, r3, r3 /* move that bit into the mod register */ 47*4882a593Smuzhiyun rsub r31, r6, r3 /* try to subtract (r30 a r6) */ 48*4882a593Smuzhiyun blti r31, mod_too_small 49*4882a593Smuzhiyun /* move the r31 to mod since the result was positive */ 50*4882a593Smuzhiyun or r3, r0, r31 51*4882a593Smuzhiyun addik r30, r30, 1 52*4882a593Smuzhiyunmod_too_small: 53*4882a593Smuzhiyun addik r29, r29, -1 54*4882a593Smuzhiyun beqi r29, loop_end 55*4882a593Smuzhiyun add r30, r30, r30 /* shift in the '1' into div */ 56*4882a593Smuzhiyun bri div2 /* div2 */ 57*4882a593Smuzhiyunloop_end: 58*4882a593Smuzhiyun bgei r28, return_here 59*4882a593Smuzhiyun brid return_here 60*4882a593Smuzhiyun rsubi r3, r3, 0 /* negate the result */ 61*4882a593Smuzhiyundiv_by_zero: 62*4882a593Smuzhiyunresult_is_zero: 63*4882a593Smuzhiyun or r3, r0, r0 /* set result to 0 [both mod as well as div are 0] */ 64*4882a593Smuzhiyunreturn_here: 65*4882a593Smuzhiyun/* restore values of csrs and that of r3 and the divisor and the dividend */ 66*4882a593Smuzhiyun lwi r28, r1, 0 67*4882a593Smuzhiyun lwi r29, r1, 4 68*4882a593Smuzhiyun lwi r30, r1, 8 69*4882a593Smuzhiyun lwi r31, r1, 12 70*4882a593Smuzhiyun rtsd r15, 8 71*4882a593Smuzhiyun addik r1, r1, 16 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun.size __modsi3, . - __modsi3 74*4882a593Smuzhiyun.end __modsi3 75