1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu> 4*4882a593Smuzhiyun * Copyright (C) 2008-2009 PetaLogix 5*4882a593Smuzhiyun * Copyright (C) 2006 Atmark Techno, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_REGISTERS_H 9*4882a593Smuzhiyun #define _ASM_MICROBLAZE_REGISTERS_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MSR_BE (1<<0) /* 0x001 */ 12*4882a593Smuzhiyun #define MSR_IE (1<<1) /* 0x002 */ 13*4882a593Smuzhiyun #define MSR_C (1<<2) /* 0x004 */ 14*4882a593Smuzhiyun #define MSR_BIP (1<<3) /* 0x008 */ 15*4882a593Smuzhiyun #define MSR_FSL (1<<4) /* 0x010 */ 16*4882a593Smuzhiyun #define MSR_ICE (1<<5) /* 0x020 */ 17*4882a593Smuzhiyun #define MSR_DZ (1<<6) /* 0x040 */ 18*4882a593Smuzhiyun #define MSR_DCE (1<<7) /* 0x080 */ 19*4882a593Smuzhiyun #define MSR_EE (1<<8) /* 0x100 */ 20*4882a593Smuzhiyun #define MSR_EIP (1<<9) /* 0x200 */ 21*4882a593Smuzhiyun #define MSR_CC (1<<31) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* Floating Point Status Register (FSR) Bits */ 24*4882a593Smuzhiyun #define FSR_IO (1<<4) /* Invalid operation */ 25*4882a593Smuzhiyun #define FSR_DZ (1<<3) /* Divide-by-zero */ 26*4882a593Smuzhiyun #define FSR_OF (1<<2) /* Overflow */ 27*4882a593Smuzhiyun #define FSR_UF (1<<1) /* Underflow */ 28*4882a593Smuzhiyun #define FSR_DO (1<<0) /* Denormalized operand error */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun # ifdef CONFIG_MMU 31*4882a593Smuzhiyun /* Machine State Register (MSR) Fields */ 32*4882a593Smuzhiyun # define MSR_UM (1<<11) /* User Mode */ 33*4882a593Smuzhiyun # define MSR_UMS (1<<12) /* User Mode Save */ 34*4882a593Smuzhiyun # define MSR_VM (1<<13) /* Virtual Mode */ 35*4882a593Smuzhiyun # define MSR_VMS (1<<14) /* Virtual Mode Save */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun # define MSR_KERNEL (MSR_EE | MSR_VM) 38*4882a593Smuzhiyun /* # define MSR_USER (MSR_KERNEL | MSR_UM | MSR_IE) */ 39*4882a593Smuzhiyun # define MSR_KERNEL_VMS (MSR_EE | MSR_VMS) 40*4882a593Smuzhiyun /* # define MSR_USER_VMS (MSR_KERNEL_VMS | MSR_UMS | MSR_IE) */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* Exception State Register (ESR) Fields */ 43*4882a593Smuzhiyun # define ESR_DIZ (1<<11) /* Zone Protection */ 44*4882a593Smuzhiyun # define ESR_S (1<<10) /* Store instruction */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun # endif /* CONFIG_MMU */ 47*4882a593Smuzhiyun #endif /* _ASM_MICROBLAZE_REGISTERS_H */ 48