1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Support for the MicroBlaze PVR (Processor Version Register) 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 - 2011 Michal Simek <monstr@monstr.eu> 6*4882a593Smuzhiyun * Copyright (C) 2007 John Williams <john.williams@petalogix.com> 7*4882a593Smuzhiyun * Copyright (C) 2007 - 2011 PetaLogix 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_PVR_H 11*4882a593Smuzhiyun #define _ASM_MICROBLAZE_PVR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define PVR_MSR_BIT 0x400 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct pvr_s { 16*4882a593Smuzhiyun unsigned pvr[12]; 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* The following taken from Xilinx's standalone BSP pvr.h */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Basic PVR mask */ 22*4882a593Smuzhiyun #define PVR0_PVR_FULL_MASK 0x80000000 23*4882a593Smuzhiyun #define PVR0_USE_BARREL_MASK 0x40000000 24*4882a593Smuzhiyun #define PVR0_USE_DIV_MASK 0x20000000 25*4882a593Smuzhiyun #define PVR0_USE_HW_MUL_MASK 0x10000000 26*4882a593Smuzhiyun #define PVR0_USE_FPU_MASK 0x08000000 27*4882a593Smuzhiyun #define PVR0_USE_EXC_MASK 0x04000000 28*4882a593Smuzhiyun #define PVR0_USE_ICACHE_MASK 0x02000000 29*4882a593Smuzhiyun #define PVR0_USE_DCACHE_MASK 0x01000000 30*4882a593Smuzhiyun #define PVR0_USE_MMU 0x00800000 31*4882a593Smuzhiyun #define PVR0_USE_BTC 0x00400000 32*4882a593Smuzhiyun #define PVR0_ENDI 0x00200000 33*4882a593Smuzhiyun #define PVR0_VERSION_MASK 0x0000FF00 34*4882a593Smuzhiyun #define PVR0_USER1_MASK 0x000000FF 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* User 2 PVR mask */ 37*4882a593Smuzhiyun #define PVR1_USER2_MASK 0xFFFFFFFF 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Configuration PVR masks */ 40*4882a593Smuzhiyun #define PVR2_D_OPB_MASK 0x80000000 /* or AXI */ 41*4882a593Smuzhiyun #define PVR2_D_LMB_MASK 0x40000000 42*4882a593Smuzhiyun #define PVR2_I_OPB_MASK 0x20000000 /* or AXI */ 43*4882a593Smuzhiyun #define PVR2_I_LMB_MASK 0x10000000 44*4882a593Smuzhiyun #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 45*4882a593Smuzhiyun #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 46*4882a593Smuzhiyun #define PVR2_D_PLB_MASK 0x02000000 /* new */ 47*4882a593Smuzhiyun #define PVR2_I_PLB_MASK 0x01000000 /* new */ 48*4882a593Smuzhiyun #define PVR2_INTERCONNECT 0x00800000 /* new */ 49*4882a593Smuzhiyun #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ 50*4882a593Smuzhiyun #define PVR2_USE_FSL_EXC 0x00040000 /* new */ 51*4882a593Smuzhiyun #define PVR2_USE_MSR_INSTR 0x00020000 52*4882a593Smuzhiyun #define PVR2_USE_PCMP_INSTR 0x00010000 53*4882a593Smuzhiyun #define PVR2_AREA_OPTIMISED 0x00008000 54*4882a593Smuzhiyun #define PVR2_USE_BARREL_MASK 0x00004000 55*4882a593Smuzhiyun #define PVR2_USE_DIV_MASK 0x00002000 56*4882a593Smuzhiyun #define PVR2_USE_HW_MUL_MASK 0x00001000 57*4882a593Smuzhiyun #define PVR2_USE_FPU_MASK 0x00000800 58*4882a593Smuzhiyun #define PVR2_USE_MUL64_MASK 0x00000400 59*4882a593Smuzhiyun #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ 60*4882a593Smuzhiyun #define PVR2_USE_IPLBEXC 0x00000100 61*4882a593Smuzhiyun #define PVR2_USE_DPLBEXC 0x00000080 62*4882a593Smuzhiyun #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 63*4882a593Smuzhiyun #define PVR2_UNALIGNED_EXC_MASK 0x00000020 64*4882a593Smuzhiyun #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 65*4882a593Smuzhiyun #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 /* or AXI */ 66*4882a593Smuzhiyun #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 /* or AXI */ 67*4882a593Smuzhiyun #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 68*4882a593Smuzhiyun #define PVR2_FPU_EXC_MASK 0x00000001 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Debug and exception PVR masks */ 71*4882a593Smuzhiyun #define PVR3_DEBUG_ENABLED_MASK 0x80000000 72*4882a593Smuzhiyun #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 73*4882a593Smuzhiyun #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 74*4882a593Smuzhiyun #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 75*4882a593Smuzhiyun #define PVR3_FSL_LINKS_MASK 0x00000380 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* ICache config PVR masks */ 78*4882a593Smuzhiyun #define PVR4_USE_ICACHE_MASK 0x80000000 /* ICU */ 79*4882a593Smuzhiyun #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* ICTS */ 80*4882a593Smuzhiyun #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 /* ICW */ 81*4882a593Smuzhiyun #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 /* ICLL */ 82*4882a593Smuzhiyun #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 /* ICBS */ 83*4882a593Smuzhiyun #define PVR4_ICACHE_ALWAYS_USED 0x00008000 /* IAU */ 84*4882a593Smuzhiyun #define PVR4_ICACHE_INTERFACE 0x00002000 /* ICI */ 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* DCache config PVR masks */ 87*4882a593Smuzhiyun #define PVR5_USE_DCACHE_MASK 0x80000000 /* DCU */ 88*4882a593Smuzhiyun #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 /* DCTS */ 89*4882a593Smuzhiyun #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 /* DCW */ 90*4882a593Smuzhiyun #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 /* DCLL */ 91*4882a593Smuzhiyun #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 /* DCBS */ 92*4882a593Smuzhiyun #define PVR5_DCACHE_ALWAYS_USED 0x00008000 /* DAU */ 93*4882a593Smuzhiyun #define PVR5_DCACHE_USE_WRITEBACK 0x00004000 /* DWB */ 94*4882a593Smuzhiyun #define PVR5_DCACHE_INTERFACE 0x00002000 /* DCI */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* ICache base address PVR mask */ 97*4882a593Smuzhiyun #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* ICache high address PVR mask */ 100*4882a593Smuzhiyun #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* DCache base address PVR mask */ 103*4882a593Smuzhiyun #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* DCache high address PVR mask */ 106*4882a593Smuzhiyun #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* Target family PVR mask */ 109*4882a593Smuzhiyun #define PVR10_TARGET_FAMILY_MASK 0xFF000000 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* MMU description */ 112*4882a593Smuzhiyun #define PVR11_USE_MMU 0xC0000000 113*4882a593Smuzhiyun #define PVR11_MMU_ITLB_SIZE 0x38000000 114*4882a593Smuzhiyun #define PVR11_MMU_DTLB_SIZE 0x07000000 115*4882a593Smuzhiyun #define PVR11_MMU_TLB_ACCESS 0x00C00000 116*4882a593Smuzhiyun #define PVR11_MMU_ZONES 0x003C0000 117*4882a593Smuzhiyun #define PVR11_MMU_PRIVINS 0x00010000 118*4882a593Smuzhiyun /* MSR Reset value PVR mask */ 119*4882a593Smuzhiyun #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* PVR access macros */ 122*4882a593Smuzhiyun #define PVR_IS_FULL(_pvr) (_pvr.pvr[0] & PVR0_PVR_FULL_MASK) 123*4882a593Smuzhiyun #define PVR_USE_BARREL(_pvr) (_pvr.pvr[0] & PVR0_USE_BARREL_MASK) 124*4882a593Smuzhiyun #define PVR_USE_DIV(_pvr) (_pvr.pvr[0] & PVR0_USE_DIV_MASK) 125*4882a593Smuzhiyun #define PVR_USE_HW_MUL(_pvr) (_pvr.pvr[0] & PVR0_USE_HW_MUL_MASK) 126*4882a593Smuzhiyun #define PVR_USE_FPU(_pvr) (_pvr.pvr[0] & PVR0_USE_FPU_MASK) 127*4882a593Smuzhiyun #define PVR_USE_FPU2(_pvr) (_pvr.pvr[2] & PVR2_USE_FPU2_MASK) 128*4882a593Smuzhiyun #define PVR_USE_ICACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_ICACHE_MASK) 129*4882a593Smuzhiyun #define PVR_USE_DCACHE(_pvr) (_pvr.pvr[0] & PVR0_USE_DCACHE_MASK) 130*4882a593Smuzhiyun #define PVR_VERSION(_pvr) ((_pvr.pvr[0] & PVR0_VERSION_MASK) >> 8) 131*4882a593Smuzhiyun #define PVR_USER1(_pvr) (_pvr.pvr[0] & PVR0_USER1_MASK) 132*4882a593Smuzhiyun #define PVR_USER2(_pvr) (_pvr.pvr[1] & PVR1_USER2_MASK) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define PVR_D_OPB(_pvr) (_pvr.pvr[2] & PVR2_D_OPB_MASK) 135*4882a593Smuzhiyun #define PVR_D_LMB(_pvr) (_pvr.pvr[2] & PVR2_D_LMB_MASK) 136*4882a593Smuzhiyun #define PVR_I_OPB(_pvr) (_pvr.pvr[2] & PVR2_I_OPB_MASK) 137*4882a593Smuzhiyun #define PVR_I_LMB(_pvr) (_pvr.pvr[2] & PVR2_I_LMB_MASK) 138*4882a593Smuzhiyun #define PVR_INTERRUPT_IS_EDGE(_pvr) \ 139*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_INTERRUPT_IS_EDGE_MASK) 140*4882a593Smuzhiyun #define PVR_EDGE_IS_POSITIVE(_pvr) \ 141*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_EDGE_IS_POSITIVE_MASK) 142*4882a593Smuzhiyun #define PVR_USE_MSR_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_MSR_INSTR) 143*4882a593Smuzhiyun #define PVR_USE_PCMP_INSTR(_pvr) (_pvr.pvr[2] & PVR2_USE_PCMP_INSTR) 144*4882a593Smuzhiyun #define PVR_AREA_OPTIMISED(_pvr) (_pvr.pvr[2] & PVR2_AREA_OPTIMISED) 145*4882a593Smuzhiyun #define PVR_USE_MUL64(_pvr) (_pvr.pvr[2] & PVR2_USE_MUL64_MASK) 146*4882a593Smuzhiyun #define PVR_OPCODE_0x0_ILLEGAL(_pvr) \ 147*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_OPCODE_0x0_ILL_MASK) 148*4882a593Smuzhiyun #define PVR_UNALIGNED_EXCEPTION(_pvr) \ 149*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_UNALIGNED_EXC_MASK) 150*4882a593Smuzhiyun #define PVR_ILL_OPCODE_EXCEPTION(_pvr) \ 151*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_ILL_OPCODE_EXC_MASK) 152*4882a593Smuzhiyun #define PVR_IOPB_BUS_EXCEPTION(_pvr) \ 153*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_IOPB_BUS_EXC_MASK) 154*4882a593Smuzhiyun #define PVR_DOPB_BUS_EXCEPTION(_pvr) \ 155*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_DOPB_BUS_EXC_MASK) 156*4882a593Smuzhiyun #define PVR_DIV_ZERO_EXCEPTION(_pvr) \ 157*4882a593Smuzhiyun (_pvr.pvr[2] & PVR2_DIV_ZERO_EXC_MASK) 158*4882a593Smuzhiyun #define PVR_FPU_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_FPU_EXC_MASK) 159*4882a593Smuzhiyun #define PVR_FSL_EXCEPTION(_pvr) (_pvr.pvr[2] & PVR2_USE_EXTEND_FSL) 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #define PVR_DEBUG_ENABLED(_pvr) (_pvr.pvr[3] & PVR3_DEBUG_ENABLED_MASK) 162*4882a593Smuzhiyun #define PVR_NUMBER_OF_PC_BRK(_pvr) \ 163*4882a593Smuzhiyun ((_pvr.pvr[3] & PVR3_NUMBER_OF_PC_BRK_MASK) >> 25) 164*4882a593Smuzhiyun #define PVR_NUMBER_OF_RD_ADDR_BRK(_pvr) \ 165*4882a593Smuzhiyun ((_pvr.pvr[3] & PVR3_NUMBER_OF_RD_ADDR_BRK_MASK) >> 19) 166*4882a593Smuzhiyun #define PVR_NUMBER_OF_WR_ADDR_BRK(_pvr) \ 167*4882a593Smuzhiyun ((_pvr.pvr[3] & PVR3_NUMBER_OF_WR_ADDR_BRK_MASK) >> 13) 168*4882a593Smuzhiyun #define PVR_FSL_LINKS(_pvr) ((_pvr.pvr[3] & PVR3_FSL_LINKS_MASK) >> 7) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define PVR_ICACHE_ADDR_TAG_BITS(_pvr) \ 171*4882a593Smuzhiyun ((_pvr.pvr[4] & PVR4_ICACHE_ADDR_TAG_BITS_MASK) >> 26) 172*4882a593Smuzhiyun #define PVR_ICACHE_USE_FSL(_pvr) \ 173*4882a593Smuzhiyun (_pvr.pvr[4] & PVR4_ICACHE_USE_FSL_MASK) 174*4882a593Smuzhiyun #define PVR_ICACHE_ALLOW_WR(_pvr) \ 175*4882a593Smuzhiyun (_pvr.pvr[4] & PVR4_ICACHE_ALLOW_WR_MASK) 176*4882a593Smuzhiyun #define PVR_ICACHE_LINE_LEN(_pvr) \ 177*4882a593Smuzhiyun (1 << ((_pvr.pvr[4] & PVR4_ICACHE_LINE_LEN_MASK) >> 21)) 178*4882a593Smuzhiyun #define PVR_ICACHE_BYTE_SIZE(_pvr) \ 179*4882a593Smuzhiyun (1 << ((_pvr.pvr[4] & PVR4_ICACHE_BYTE_SIZE_MASK) >> 16)) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define PVR_DCACHE_ADDR_TAG_BITS(_pvr) \ 182*4882a593Smuzhiyun ((_pvr.pvr[5] & PVR5_DCACHE_ADDR_TAG_BITS_MASK) >> 26) 183*4882a593Smuzhiyun #define PVR_DCACHE_USE_FSL(_pvr) (_pvr.pvr[5] & PVR5_DCACHE_USE_FSL_MASK) 184*4882a593Smuzhiyun #define PVR_DCACHE_ALLOW_WR(_pvr) \ 185*4882a593Smuzhiyun (_pvr.pvr[5] & PVR5_DCACHE_ALLOW_WR_MASK) 186*4882a593Smuzhiyun /* FIXME two shifts on one line needs any comment */ 187*4882a593Smuzhiyun #define PVR_DCACHE_LINE_LEN(_pvr) \ 188*4882a593Smuzhiyun (1 << ((_pvr.pvr[5] & PVR5_DCACHE_LINE_LEN_MASK) >> 21)) 189*4882a593Smuzhiyun #define PVR_DCACHE_BYTE_SIZE(_pvr) \ 190*4882a593Smuzhiyun (1 << ((_pvr.pvr[5] & PVR5_DCACHE_BYTE_SIZE_MASK) >> 16)) 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define PVR_DCACHE_USE_WRITEBACK(_pvr) \ 193*4882a593Smuzhiyun ((_pvr.pvr[5] & PVR5_DCACHE_USE_WRITEBACK) >> 14) 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define PVR_ICACHE_BASEADDR(_pvr) \ 196*4882a593Smuzhiyun (_pvr.pvr[6] & PVR6_ICACHE_BASEADDR_MASK) 197*4882a593Smuzhiyun #define PVR_ICACHE_HIGHADDR(_pvr) \ 198*4882a593Smuzhiyun (_pvr.pvr[7] & PVR7_ICACHE_HIGHADDR_MASK) 199*4882a593Smuzhiyun #define PVR_DCACHE_BASEADDR(_pvr) \ 200*4882a593Smuzhiyun (_pvr.pvr[8] & PVR8_DCACHE_BASEADDR_MASK) 201*4882a593Smuzhiyun #define PVR_DCACHE_HIGHADDR(_pvr) \ 202*4882a593Smuzhiyun (_pvr.pvr[9] & PVR9_DCACHE_HIGHADDR_MASK) 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define PVR_TARGET_FAMILY(_pvr) \ 205*4882a593Smuzhiyun ((_pvr.pvr[10] & PVR10_TARGET_FAMILY_MASK) >> 24) 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define PVR_MSR_RESET_VALUE(_pvr) \ 208*4882a593Smuzhiyun (_pvr.pvr[11] & PVR11_MSR_RESET_VALUE_MASK) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* mmu */ 211*4882a593Smuzhiyun #define PVR_USE_MMU(_pvr) ((_pvr.pvr[11] & PVR11_USE_MMU) >> 30) 212*4882a593Smuzhiyun #define PVR_MMU_ITLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_ITLB_SIZE) 213*4882a593Smuzhiyun #define PVR_MMU_DTLB_SIZE(_pvr) (_pvr.pvr[11] & PVR11_MMU_DTLB_SIZE) 214*4882a593Smuzhiyun #define PVR_MMU_TLB_ACCESS(_pvr) (_pvr.pvr[11] & PVR11_MMU_TLB_ACCESS) 215*4882a593Smuzhiyun #define PVR_MMU_ZONES(_pvr) (_pvr.pvr[11] & PVR11_MMU_ZONES) 216*4882a593Smuzhiyun #define PVR_MMU_PRIVINS(pvr) (pvr.pvr[11] & PVR11_MMU_PRIVINS) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* endian */ 219*4882a593Smuzhiyun #define PVR_ENDIAN(_pvr) (_pvr.pvr[0] & PVR0_ENDI) 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun int cpu_has_pvr(void); 222*4882a593Smuzhiyun void get_pvr(struct pvr_s *pvr); 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun #endif /* _ASM_MICROBLAZE_PVR_H */ 225