1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_PCI_BRIDGE_H
3*4882a593Smuzhiyun #define _ASM_MICROBLAZE_PCI_BRIDGE_H
4*4882a593Smuzhiyun #ifdef __KERNEL__
5*4882a593Smuzhiyun /*
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/pci.h>
8*4882a593Smuzhiyun #include <linux/list.h>
9*4882a593Smuzhiyun #include <linux/ioport.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun struct device_node;
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifdef CONFIG_PCI
14*4882a593Smuzhiyun extern struct list_head hose_list;
15*4882a593Smuzhiyun extern int pcibios_vaddr_is_ioport(void __iomem *address);
16*4882a593Smuzhiyun #else
pcibios_vaddr_is_ioport(void __iomem * address)17*4882a593Smuzhiyun static inline int pcibios_vaddr_is_ioport(void __iomem *address)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun return 0;
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun #endif
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun * Structure of a PCI controller (host bridge)
25*4882a593Smuzhiyun */
26*4882a593Smuzhiyun struct pci_controller {
27*4882a593Smuzhiyun struct pci_bus *bus;
28*4882a593Smuzhiyun char is_dynamic;
29*4882a593Smuzhiyun struct device_node *dn;
30*4882a593Smuzhiyun struct list_head list_node;
31*4882a593Smuzhiyun struct device *parent;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun int first_busno;
34*4882a593Smuzhiyun int last_busno;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun int self_busno;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun void __iomem *io_base_virt;
39*4882a593Smuzhiyun resource_size_t io_base_phys;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun resource_size_t pci_io_size;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Some machines (PReP) have a non 1:1 mapping of
44*4882a593Smuzhiyun * the PCI memory space in the CPU bus space
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun resource_size_t pci_mem_offset;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* Some machines have a special region to forward the ISA
49*4882a593Smuzhiyun * "memory" cycles such as VGA memory regions. Left to 0
50*4882a593Smuzhiyun * if unsupported
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun resource_size_t isa_mem_phys;
53*4882a593Smuzhiyun resource_size_t isa_mem_size;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct pci_ops *ops;
56*4882a593Smuzhiyun unsigned int __iomem *cfg_addr;
57*4882a593Smuzhiyun void __iomem *cfg_data;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun * Used for variants of PCI indirect handling and possible quirks:
61*4882a593Smuzhiyun * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
62*4882a593Smuzhiyun * EXT_REG - provides access to PCI-e extended registers
63*4882a593Smuzhiyun * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
64*4882a593Smuzhiyun * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
65*4882a593Smuzhiyun * to determine which bus number to match on when generating type0
66*4882a593Smuzhiyun * config cycles
67*4882a593Smuzhiyun * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
68*4882a593Smuzhiyun * hanging if we don't have link and try to do config cycles to
69*4882a593Smuzhiyun * anything but the PHB. Only allow talking to the PHB if this is
70*4882a593Smuzhiyun * set.
71*4882a593Smuzhiyun * BIG_ENDIAN - cfg_addr is a big endian register
72*4882a593Smuzhiyun * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs
73*4882a593Smuzhiyun * on the PLB4. Effectively disable MRM commands by setting this.
74*4882a593Smuzhiyun */
75*4882a593Smuzhiyun #define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
76*4882a593Smuzhiyun #define INDIRECT_TYPE_EXT_REG 0x00000002
77*4882a593Smuzhiyun #define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
78*4882a593Smuzhiyun #define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
79*4882a593Smuzhiyun #define INDIRECT_TYPE_BIG_ENDIAN 0x00000010
80*4882a593Smuzhiyun #define INDIRECT_TYPE_BROKEN_MRM 0x00000020
81*4882a593Smuzhiyun u32 indirect_type;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Currently, we limit ourselves to 1 IO range and 3 mem
84*4882a593Smuzhiyun * ranges since the common pci_bus structure can't handle more
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun struct resource io_resource;
87*4882a593Smuzhiyun struct resource mem_resources[3];
88*4882a593Smuzhiyun int global_number; /* PCI domain number */
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #ifdef CONFIG_PCI
pci_bus_to_host(const struct pci_bus * bus)92*4882a593Smuzhiyun static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun return bus->sysdata;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
isa_vaddr_is_ioport(void __iomem * address)97*4882a593Smuzhiyun static inline int isa_vaddr_is_ioport(void __iomem *address)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun /* No specific ISA handling on ppc32 at this stage, it
100*4882a593Smuzhiyun * all goes through PCI
101*4882a593Smuzhiyun */
102*4882a593Smuzhiyun return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun #endif /* CONFIG_PCI */
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* These are used for config access before all the PCI probing
107*4882a593Smuzhiyun has been done. */
108*4882a593Smuzhiyun extern int early_read_config_byte(struct pci_controller *hose, int bus,
109*4882a593Smuzhiyun int dev_fn, int where, u8 *val);
110*4882a593Smuzhiyun extern int early_read_config_word(struct pci_controller *hose, int bus,
111*4882a593Smuzhiyun int dev_fn, int where, u16 *val);
112*4882a593Smuzhiyun extern int early_read_config_dword(struct pci_controller *hose, int bus,
113*4882a593Smuzhiyun int dev_fn, int where, u32 *val);
114*4882a593Smuzhiyun extern int early_write_config_byte(struct pci_controller *hose, int bus,
115*4882a593Smuzhiyun int dev_fn, int where, u8 val);
116*4882a593Smuzhiyun extern int early_write_config_word(struct pci_controller *hose, int bus,
117*4882a593Smuzhiyun int dev_fn, int where, u16 val);
118*4882a593Smuzhiyun extern int early_write_config_dword(struct pci_controller *hose, int bus,
119*4882a593Smuzhiyun int dev_fn, int where, u32 val);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun extern int early_find_capability(struct pci_controller *hose, int bus,
122*4882a593Smuzhiyun int dev_fn, int cap);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun extern void setup_indirect_pci(struct pci_controller *hose,
125*4882a593Smuzhiyun resource_size_t cfg_addr,
126*4882a593Smuzhiyun resource_size_t cfg_data, u32 flags);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* Get the PCI host controller for an OF device */
129*4882a593Smuzhiyun extern struct pci_controller *pci_find_hose_for_OF_device(
130*4882a593Smuzhiyun struct device_node *node);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun /* Fill up host controller resources from the OF node */
133*4882a593Smuzhiyun extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
134*4882a593Smuzhiyun struct device_node *dev, int primary);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* Allocate & free a PCI host bridge structure */
137*4882a593Smuzhiyun extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
138*4882a593Smuzhiyun extern void pcibios_free_controller(struct pci_controller *phb);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #endif /* __KERNEL__ */
141*4882a593Smuzhiyun #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */
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