1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Generic support for queying CPU info 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu> 6*4882a593Smuzhiyun * Copyright (C) 2007-2009 PetaLogix 7*4882a593Smuzhiyun * Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef _ASM_MICROBLAZE_CPUINFO_H 11*4882a593Smuzhiyun #define _ASM_MICROBLAZE_CPUINFO_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/of.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* CPU Version and FPGA Family code conversion table type */ 16*4882a593Smuzhiyun struct cpu_ver_key { 17*4882a593Smuzhiyun const char *s; 18*4882a593Smuzhiyun const unsigned k; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun extern const struct cpu_ver_key cpu_ver_lookup[]; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct family_string_key { 24*4882a593Smuzhiyun const char *s; 25*4882a593Smuzhiyun const unsigned k; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun extern const struct family_string_key family_string_lookup[]; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct cpuinfo { 31*4882a593Smuzhiyun /* Core CPU configuration */ 32*4882a593Smuzhiyun u32 use_instr; 33*4882a593Smuzhiyun u32 use_mult; 34*4882a593Smuzhiyun u32 use_fpu; 35*4882a593Smuzhiyun u32 use_exc; 36*4882a593Smuzhiyun u32 ver_code; 37*4882a593Smuzhiyun u32 mmu; 38*4882a593Smuzhiyun u32 mmu_privins; 39*4882a593Smuzhiyun u32 endian; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* CPU caches */ 42*4882a593Smuzhiyun u32 use_icache; 43*4882a593Smuzhiyun u32 icache_tagbits; 44*4882a593Smuzhiyun u32 icache_write; 45*4882a593Smuzhiyun u32 icache_line_length; 46*4882a593Smuzhiyun u32 icache_size; 47*4882a593Smuzhiyun unsigned long icache_base; 48*4882a593Smuzhiyun unsigned long icache_high; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun u32 use_dcache; 51*4882a593Smuzhiyun u32 dcache_tagbits; 52*4882a593Smuzhiyun u32 dcache_write; 53*4882a593Smuzhiyun u32 dcache_line_length; 54*4882a593Smuzhiyun u32 dcache_size; 55*4882a593Smuzhiyun u32 dcache_wb; 56*4882a593Smuzhiyun unsigned long dcache_base; 57*4882a593Smuzhiyun unsigned long dcache_high; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Bus connections */ 60*4882a593Smuzhiyun u32 use_dopb; 61*4882a593Smuzhiyun u32 use_iopb; 62*4882a593Smuzhiyun u32 use_dlmb; 63*4882a593Smuzhiyun u32 use_ilmb; 64*4882a593Smuzhiyun u32 num_fsl; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* CPU interrupt line info */ 67*4882a593Smuzhiyun u32 irq_edge; 68*4882a593Smuzhiyun u32 irq_positive; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun u32 area_optimised; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* HW debug support */ 73*4882a593Smuzhiyun u32 hw_debug; 74*4882a593Smuzhiyun u32 num_pc_brk; 75*4882a593Smuzhiyun u32 num_rd_brk; 76*4882a593Smuzhiyun u32 num_wr_brk; 77*4882a593Smuzhiyun u32 cpu_clock_freq; /* store real freq of cpu */ 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* FPGA family */ 80*4882a593Smuzhiyun u32 fpga_family_code; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* User define */ 83*4882a593Smuzhiyun u32 pvr_user1; 84*4882a593Smuzhiyun u32 pvr_user2; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun extern struct cpuinfo cpuinfo; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* fwd declarations of the various CPUinfo populators */ 90*4882a593Smuzhiyun void setup_cpuinfo(void); 91*4882a593Smuzhiyun void setup_cpuinfo_clk(void); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu); 94*4882a593Smuzhiyun void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu); 95*4882a593Smuzhiyun fcpu(struct device_node * cpu,char * n)96*4882a593Smuzhiyunstatic inline unsigned int fcpu(struct device_node *cpu, char *n) 97*4882a593Smuzhiyun { 98*4882a593Smuzhiyun u32 val = 0; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun of_property_read_u32(cpu, n, &val); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun return val; 103*4882a593Smuzhiyun } 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* _ASM_MICROBLAZE_CPUINFO_H */ 106