xref: /OK3568_Linux_fs/kernel/arch/m68k/mac/psc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *	Apple Peripheral System Controller (PSC)
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  *	The PSC is used on the AV Macs to control IO functions not handled
6*4882a593Smuzhiyun  *	by the VIAs (Ethernet, DSP, SCC).
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * TO DO:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * Try to figure out what's going on in pIFR5 and pIFR6. There seem to be
11*4882a593Smuzhiyun  * persisant interrupt conditions in those registers and I have no idea what
12*4882a593Smuzhiyun  * they are. Granted it doesn't affect since we're not enabling any interrupts
13*4882a593Smuzhiyun  * on those levels at the moment, but it would be nice to know. I have a feeling
14*4882a593Smuzhiyun  * they aren't actually interrupt lines but data lines (to the DSP?)
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/mm.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun #include <linux/init.h>
22*4882a593Smuzhiyun #include <linux/irq.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <asm/traps.h>
25*4882a593Smuzhiyun #include <asm/macintosh.h>
26*4882a593Smuzhiyun #include <asm/macints.h>
27*4882a593Smuzhiyun #include <asm/mac_psc.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define DEBUG_PSC
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun volatile __u8 *psc;
32*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(psc);
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun  * Debugging dump, used in various places to see what's going on.
36*4882a593Smuzhiyun  */
37*4882a593Smuzhiyun 
psc_debug_dump(void)38*4882a593Smuzhiyun static void psc_debug_dump(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	int	i;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	if (!psc)
43*4882a593Smuzhiyun 		return;
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun 	for (i = 0x30 ; i < 0x70 ; i += 0x10) {
46*4882a593Smuzhiyun 		printk(KERN_DEBUG "PSC #%d:  IFR = 0x%02X IER = 0x%02X\n",
47*4882a593Smuzhiyun 			i >> 4,
48*4882a593Smuzhiyun 			(int) psc_read_byte(pIFRbase + i),
49*4882a593Smuzhiyun 			(int) psc_read_byte(pIERbase + i));
50*4882a593Smuzhiyun 	}
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun  * Try to kill all DMA channels on the PSC. Not sure how this his
55*4882a593Smuzhiyun  * supposed to work; this is code lifted from macmace.c and then
56*4882a593Smuzhiyun  * expanded to cover what I think are the other 7 channels.
57*4882a593Smuzhiyun  */
58*4882a593Smuzhiyun 
psc_dma_die_die_die(void)59*4882a593Smuzhiyun static __init void psc_dma_die_die_die(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	int i;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	for (i = 0 ; i < 9 ; i++) {
64*4882a593Smuzhiyun 		psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800);
65*4882a593Smuzhiyun 		psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000);
66*4882a593Smuzhiyun 		psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100);
67*4882a593Smuzhiyun 		psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100);
68*4882a593Smuzhiyun 	}
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * Initialize the PSC. For now this just involves shutting down all
73*4882a593Smuzhiyun  * interrupt sources using the IERs.
74*4882a593Smuzhiyun  */
75*4882a593Smuzhiyun 
psc_init(void)76*4882a593Smuzhiyun void __init psc_init(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	int i;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	if (macintosh_config->ident != MAC_MODEL_C660
81*4882a593Smuzhiyun 	 && macintosh_config->ident != MAC_MODEL_Q840)
82*4882a593Smuzhiyun 	{
83*4882a593Smuzhiyun 		psc = NULL;
84*4882a593Smuzhiyun 		return;
85*4882a593Smuzhiyun 	}
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	/*
88*4882a593Smuzhiyun 	 * The PSC is always at the same spot, but using psc
89*4882a593Smuzhiyun 	 * keeps things consistent with the psc_xxxx functions.
90*4882a593Smuzhiyun 	 */
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	psc = (void *) PSC_BASE;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	pr_debug("PSC detected at %p\n", psc);
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun 	psc_dma_die_die_die();
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #ifdef DEBUG_PSC
99*4882a593Smuzhiyun 	psc_debug_dump();
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun 	/*
102*4882a593Smuzhiyun 	 * Mask and clear all possible interrupts
103*4882a593Smuzhiyun 	 */
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	for (i = 0x30 ; i < 0x70 ; i += 0x10) {
106*4882a593Smuzhiyun 		psc_write_byte(pIERbase + i, 0x0F);
107*4882a593Smuzhiyun 		psc_write_byte(pIFRbase + i, 0x0F);
108*4882a593Smuzhiyun 	}
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun  * PSC interrupt handler. It's a lot like the VIA interrupt handler.
113*4882a593Smuzhiyun  */
114*4882a593Smuzhiyun 
psc_irq(struct irq_desc * desc)115*4882a593Smuzhiyun static void psc_irq(struct irq_desc *desc)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun 	unsigned int offset = (unsigned int)irq_desc_get_handler_data(desc);
118*4882a593Smuzhiyun 	unsigned int irq = irq_desc_get_irq(desc);
119*4882a593Smuzhiyun 	int pIFR	= pIFRbase + offset;
120*4882a593Smuzhiyun 	int pIER	= pIERbase + offset;
121*4882a593Smuzhiyun 	int irq_num;
122*4882a593Smuzhiyun 	unsigned char irq_bit, events;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	events = psc_read_byte(pIFR) & psc_read_byte(pIER) & 0xF;
125*4882a593Smuzhiyun 	if (!events)
126*4882a593Smuzhiyun 		return;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	irq_num = irq << 3;
129*4882a593Smuzhiyun 	irq_bit = 1;
130*4882a593Smuzhiyun 	do {
131*4882a593Smuzhiyun 		if (events & irq_bit) {
132*4882a593Smuzhiyun 			psc_write_byte(pIFR, irq_bit);
133*4882a593Smuzhiyun 			generic_handle_irq(irq_num);
134*4882a593Smuzhiyun 		}
135*4882a593Smuzhiyun 		irq_num++;
136*4882a593Smuzhiyun 		irq_bit <<= 1;
137*4882a593Smuzhiyun 	} while (events >= irq_bit);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun  * Register the PSC interrupt dispatchers for autovector interrupts 3-6.
142*4882a593Smuzhiyun  */
143*4882a593Smuzhiyun 
psc_register_interrupts(void)144*4882a593Smuzhiyun void __init psc_register_interrupts(void)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	irq_set_chained_handler_and_data(IRQ_AUTO_3, psc_irq, (void *)0x30);
147*4882a593Smuzhiyun 	irq_set_chained_handler_and_data(IRQ_AUTO_4, psc_irq, (void *)0x40);
148*4882a593Smuzhiyun 	irq_set_chained_handler_and_data(IRQ_AUTO_5, psc_irq, (void *)0x50);
149*4882a593Smuzhiyun 	irq_set_chained_handler_and_data(IRQ_AUTO_6, psc_irq, (void *)0x60);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
psc_irq_enable(int irq)152*4882a593Smuzhiyun void psc_irq_enable(int irq) {
153*4882a593Smuzhiyun 	int irq_src	= IRQ_SRC(irq);
154*4882a593Smuzhiyun 	int irq_idx	= IRQ_IDX(irq);
155*4882a593Smuzhiyun 	int pIER	= pIERbase + (irq_src << 4);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	psc_write_byte(pIER, (1 << irq_idx) | 0x80);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
psc_irq_disable(int irq)160*4882a593Smuzhiyun void psc_irq_disable(int irq) {
161*4882a593Smuzhiyun 	int irq_src	= IRQ_SRC(irq);
162*4882a593Smuzhiyun 	int irq_idx	= IRQ_IDX(irq);
163*4882a593Smuzhiyun 	int pIER	= pIERbase + (irq_src << 4);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	psc_write_byte(pIER, 1 << irq_idx);
166*4882a593Smuzhiyun }
167