1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * contains some Q40 related interrupt definitions 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define Q40_IRQ_MAX (34) 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define Q40_IRQ_SAMPLE (34) 9*4882a593Smuzhiyun #define Q40_IRQ_KEYBOARD (32) 10*4882a593Smuzhiyun #define Q40_IRQ_FRAME (33) 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* masks for interrupt regiosters*/ 14*4882a593Smuzhiyun /* internal, IIRQ_REG */ 15*4882a593Smuzhiyun #define Q40_IRQ_KEYB_MASK (2) 16*4882a593Smuzhiyun #define Q40_IRQ_SER_MASK (1<<2) 17*4882a593Smuzhiyun #define Q40_IRQ_FRAME_MASK (1<<3) 18*4882a593Smuzhiyun #define Q40_IRQ_EXT_MASK (1<<4) /* is a EIRQ */ 19*4882a593Smuzhiyun /* eirq, EIRQ_REG */ 20*4882a593Smuzhiyun #define Q40_IRQ3_MASK (1) 21*4882a593Smuzhiyun #define Q40_IRQ4_MASK (1<<1) 22*4882a593Smuzhiyun #define Q40_IRQ5_MASK (1<<2) 23*4882a593Smuzhiyun #define Q40_IRQ6_MASK (1<<3) 24*4882a593Smuzhiyun #define Q40_IRQ7_MASK (1<<4) 25*4882a593Smuzhiyun #define Q40_IRQ10_MASK (1<<5) 26*4882a593Smuzhiyun #define Q40_IRQ14_MASK (1<<6) 27*4882a593Smuzhiyun #define Q40_IRQ15_MASK (1<<7) 28