1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Q40 master Chip Control 4*4882a593Smuzhiyun * RTC stuff merged for compactness. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _Q40_MASTER_H 8*4882a593Smuzhiyun #define _Q40_MASTER_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/raw_io.h> 11*4882a593Smuzhiyun #include <asm/kmap.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define q40_master_addr 0xff000000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define IIRQ_REG 0x0 /* internal IRQ reg */ 16*4882a593Smuzhiyun #define EIRQ_REG 0x4 /* external ... */ 17*4882a593Smuzhiyun #define KEYCODE_REG 0x1c /* value of received scancode */ 18*4882a593Smuzhiyun #define DISPLAY_CONTROL_REG 0x18 19*4882a593Smuzhiyun #define FRAME_CLEAR_REG 0x24 20*4882a593Smuzhiyun #define LED_REG 0x30 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define Q40_LED_ON() master_outb(1,LED_REG) 23*4882a593Smuzhiyun #define Q40_LED_OFF() master_outb(0,LED_REG) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define INTERRUPT_REG IIRQ_REG /* "native" ints */ 26*4882a593Smuzhiyun #define KEY_IRQ_ENABLE_REG 0x08 /**/ 27*4882a593Smuzhiyun #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */ 30*4882a593Smuzhiyun #define SAMPLE_RATE_REG 0x2c 31*4882a593Smuzhiyun #define SAMPLE_CLEAR_REG 0x28 32*4882a593Smuzhiyun #define SAMPLE_LOW 0x00 33*4882a593Smuzhiyun #define SAMPLE_HIGH 0x01 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #if 0 38*4882a593Smuzhiyun #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */ 39*4882a593Smuzhiyun #endif 40*4882a593Smuzhiyun #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define master_inb(_reg_) in_8((unsigned char *)q40_master_addr+_reg_) 44*4882a593Smuzhiyun #define master_outb(_b_,_reg_) out_8((unsigned char *)q40_master_addr+_reg_,_b_) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* RTC defines */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define Q40_RTC_BASE (0xff021ffc) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define Q40_RTC_YEAR (*(volatile unsigned char *)(Q40_RTC_BASE+0)) 51*4882a593Smuzhiyun #define Q40_RTC_MNTH (*(volatile unsigned char *)(Q40_RTC_BASE-4)) 52*4882a593Smuzhiyun #define Q40_RTC_DATE (*(volatile unsigned char *)(Q40_RTC_BASE-8)) 53*4882a593Smuzhiyun #define Q40_RTC_DOW (*(volatile unsigned char *)(Q40_RTC_BASE-12)) 54*4882a593Smuzhiyun #define Q40_RTC_HOUR (*(volatile unsigned char *)(Q40_RTC_BASE-16)) 55*4882a593Smuzhiyun #define Q40_RTC_MINS (*(volatile unsigned char *)(Q40_RTC_BASE-20)) 56*4882a593Smuzhiyun #define Q40_RTC_SECS (*(volatile unsigned char *)(Q40_RTC_BASE-24)) 57*4882a593Smuzhiyun #define Q40_RTC_CTRL (*(volatile unsigned char *)(Q40_RTC_BASE-28)) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* some control bits */ 60*4882a593Smuzhiyun #define Q40_RTC_READ 64 /* prepare for reading */ 61*4882a593Smuzhiyun #define Q40_RTC_WRITE 128 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* define some Q40 specific ints */ 64*4882a593Smuzhiyun #include <asm/q40ints.h> 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* misc defs */ 67*4882a593Smuzhiyun #define DAC_LEFT ((unsigned char *)0xff008000) 68*4882a593Smuzhiyun #define DAC_RIGHT ((unsigned char *)0xff008004) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* _Q40_MASTER_H */ 71