1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _M68K_MVME16xHW_H_ 3*4882a593Smuzhiyun #define _M68K_MVME16xHW_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/irq.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun typedef struct { 9*4882a593Smuzhiyun u_char ack_icr, 10*4882a593Smuzhiyun flt_icr, 11*4882a593Smuzhiyun sel_icr, 12*4882a593Smuzhiyun pe_icr, 13*4882a593Smuzhiyun bsy_icr, 14*4882a593Smuzhiyun spare1, 15*4882a593Smuzhiyun isr, 16*4882a593Smuzhiyun cr, 17*4882a593Smuzhiyun spare2, 18*4882a593Smuzhiyun spare3, 19*4882a593Smuzhiyun spare4, 20*4882a593Smuzhiyun data; 21*4882a593Smuzhiyun } MVMElp, *MVMElpPtr; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define MVME_LPR_BASE 0xfff42030 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define mvmelp ((*(volatile MVMElpPtr)(MVME_LPR_BASE))) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun typedef struct { 28*4882a593Smuzhiyun unsigned char 29*4882a593Smuzhiyun ctrl, 30*4882a593Smuzhiyun bcd_sec, 31*4882a593Smuzhiyun bcd_min, 32*4882a593Smuzhiyun bcd_hr, 33*4882a593Smuzhiyun bcd_dow, 34*4882a593Smuzhiyun bcd_dom, 35*4882a593Smuzhiyun bcd_mth, 36*4882a593Smuzhiyun bcd_year; 37*4882a593Smuzhiyun } MK48T08_t, *MK48T08ptr_t; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define RTC_WRITE 0x80 40*4882a593Smuzhiyun #define RTC_READ 0x40 41*4882a593Smuzhiyun #define RTC_STOP 0x20 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MVME_RTC_BASE 0xfffc1ff8 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define MVME_I596_BASE 0xfff46000 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MVME_SCC_A_ADDR 0xfff45005 48*4882a593Smuzhiyun #define MVME_SCC_B_ADDR 0xfff45001 49*4882a593Smuzhiyun #define MVME_SCC_PCLK 10000000 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define MVME162_IRQ_TYPE_PRIO 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define MVME167_IRQ_PRN (IRQ_USER+20) 54*4882a593Smuzhiyun #define MVME16x_IRQ_I596 (IRQ_USER+23) 55*4882a593Smuzhiyun #define MVME16x_IRQ_SCSI (IRQ_USER+21) 56*4882a593Smuzhiyun #define MVME16x_IRQ_FLY (IRQ_USER+63) 57*4882a593Smuzhiyun #define MVME167_IRQ_SER_ERR (IRQ_USER+28) 58*4882a593Smuzhiyun #define MVME167_IRQ_SER_MODEM (IRQ_USER+29) 59*4882a593Smuzhiyun #define MVME167_IRQ_SER_TX (IRQ_USER+30) 60*4882a593Smuzhiyun #define MVME167_IRQ_SER_RX (IRQ_USER+31) 61*4882a593Smuzhiyun #define MVME16x_IRQ_TIMER (IRQ_USER+25) 62*4882a593Smuzhiyun #define MVME167_IRQ_ABORT (IRQ_USER+46) 63*4882a593Smuzhiyun #define MVME162_IRQ_ABORT (IRQ_USER+30) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* SCC interrupts, for MVME162 */ 66*4882a593Smuzhiyun #define MVME162_IRQ_SCC_BASE (IRQ_USER+0) 67*4882a593Smuzhiyun #define MVME162_IRQ_SCCB_TX (IRQ_USER+0) 68*4882a593Smuzhiyun #define MVME162_IRQ_SCCB_STAT (IRQ_USER+2) 69*4882a593Smuzhiyun #define MVME162_IRQ_SCCB_RX (IRQ_USER+4) 70*4882a593Smuzhiyun #define MVME162_IRQ_SCCB_SPCOND (IRQ_USER+6) 71*4882a593Smuzhiyun #define MVME162_IRQ_SCCA_TX (IRQ_USER+8) 72*4882a593Smuzhiyun #define MVME162_IRQ_SCCA_STAT (IRQ_USER+10) 73*4882a593Smuzhiyun #define MVME162_IRQ_SCCA_RX (IRQ_USER+12) 74*4882a593Smuzhiyun #define MVME162_IRQ_SCCA_SPCOND (IRQ_USER+14) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* MVME162 version register */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define MVME162_VERSION_REG 0xfff4202e 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun extern unsigned short mvme16x_config; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Lower 8 bits must match the revision register in the MC2 chip */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define MVME16x_CONFIG_SPEED_32 0x0001 85*4882a593Smuzhiyun #define MVME16x_CONFIG_NO_VMECHIP2 0x0002 86*4882a593Smuzhiyun #define MVME16x_CONFIG_NO_SCSICHIP 0x0004 87*4882a593Smuzhiyun #define MVME16x_CONFIG_NO_ETHERNET 0x0008 88*4882a593Smuzhiyun #define MVME16x_CONFIG_GOT_FPU 0x0010 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define MVME16x_CONFIG_GOT_LP 0x0100 91*4882a593Smuzhiyun #define MVME16x_CONFIG_GOT_CD2401 0x0200 92*4882a593Smuzhiyun #define MVME16x_CONFIG_GOT_SCCA 0x0400 93*4882a593Smuzhiyun #define MVME16x_CONFIG_GOT_SCCB 0x0800 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #endif 96