1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _MVME147HW_H_ 3*4882a593Smuzhiyun #define _MVME147HW_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <asm/irq.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun typedef struct { 8*4882a593Smuzhiyun unsigned char 9*4882a593Smuzhiyun ctrl, 10*4882a593Smuzhiyun bcd_sec, 11*4882a593Smuzhiyun bcd_min, 12*4882a593Smuzhiyun bcd_hr, 13*4882a593Smuzhiyun bcd_dow, 14*4882a593Smuzhiyun bcd_dom, 15*4882a593Smuzhiyun bcd_mth, 16*4882a593Smuzhiyun bcd_year; 17*4882a593Smuzhiyun } MK48T02; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define RTC_WRITE 0x80 20*4882a593Smuzhiyun #define RTC_READ 0x40 21*4882a593Smuzhiyun #define RTC_STOP 0x20 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define m147_rtc ((MK48T02 * volatile)0xfffe07f8) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct pcc_regs { 27*4882a593Smuzhiyun volatile u_long dma_tadr; 28*4882a593Smuzhiyun volatile u_long dma_dadr; 29*4882a593Smuzhiyun volatile u_long dma_bcr; 30*4882a593Smuzhiyun volatile u_long dma_hr; 31*4882a593Smuzhiyun volatile u_short t1_preload; 32*4882a593Smuzhiyun volatile u_short t1_count; 33*4882a593Smuzhiyun volatile u_short t2_preload; 34*4882a593Smuzhiyun volatile u_short t2_count; 35*4882a593Smuzhiyun volatile u_char t1_int_cntrl; 36*4882a593Smuzhiyun volatile u_char t1_cntrl; 37*4882a593Smuzhiyun volatile u_char t2_int_cntrl; 38*4882a593Smuzhiyun volatile u_char t2_cntrl; 39*4882a593Smuzhiyun volatile u_char ac_fail; 40*4882a593Smuzhiyun volatile u_char watchdog; 41*4882a593Smuzhiyun volatile u_char lpt_intr; 42*4882a593Smuzhiyun volatile u_char lpt_cntrl; 43*4882a593Smuzhiyun volatile u_char dma_intr; 44*4882a593Smuzhiyun volatile u_char dma_cntrl; 45*4882a593Smuzhiyun volatile u_char bus_error; 46*4882a593Smuzhiyun volatile u_char dma_status; 47*4882a593Smuzhiyun volatile u_char abort; 48*4882a593Smuzhiyun volatile u_char ta_fnctl; 49*4882a593Smuzhiyun volatile u_char serial_cntrl; 50*4882a593Smuzhiyun volatile u_char general_cntrl; 51*4882a593Smuzhiyun volatile u_char lan_cntrl; 52*4882a593Smuzhiyun volatile u_char general_status; 53*4882a593Smuzhiyun volatile u_char scsi_interrupt; 54*4882a593Smuzhiyun volatile u_char slave; 55*4882a593Smuzhiyun volatile u_char soft1_cntrl; 56*4882a593Smuzhiyun volatile u_char int_base; 57*4882a593Smuzhiyun volatile u_char soft2_cntrl; 58*4882a593Smuzhiyun volatile u_char revision_level; 59*4882a593Smuzhiyun volatile u_char lpt_data; 60*4882a593Smuzhiyun volatile u_char lpt_status; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define m147_pcc ((struct pcc_regs * volatile)0xfffe1000) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #define PCC_INT_ENAB 0x08 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define PCC_TIMER_INT_CLR 0x80 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define PCC_TIMER_TIC_EN 0x01 71*4882a593Smuzhiyun #define PCC_TIMER_COC_EN 0x02 72*4882a593Smuzhiyun #define PCC_TIMER_CLR_OVF 0x04 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define PCC_LEVEL_ABORT 0x07 75*4882a593Smuzhiyun #define PCC_LEVEL_SERIAL 0x04 76*4882a593Smuzhiyun #define PCC_LEVEL_ETH 0x04 77*4882a593Smuzhiyun #define PCC_LEVEL_TIMER1 0x04 78*4882a593Smuzhiyun #define PCC_LEVEL_SCSI_PORT 0x04 79*4882a593Smuzhiyun #define PCC_LEVEL_SCSI_DMA 0x04 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define PCC_IRQ_AC_FAIL (IRQ_USER+0) 82*4882a593Smuzhiyun #define PCC_IRQ_BERR (IRQ_USER+1) 83*4882a593Smuzhiyun #define PCC_IRQ_ABORT (IRQ_USER+2) 84*4882a593Smuzhiyun /* #define PCC_IRQ_SERIAL (IRQ_USER+3) */ 85*4882a593Smuzhiyun #define PCC_IRQ_PRINTER (IRQ_USER+7) 86*4882a593Smuzhiyun #define PCC_IRQ_TIMER1 (IRQ_USER+8) 87*4882a593Smuzhiyun #define PCC_IRQ_TIMER2 (IRQ_USER+9) 88*4882a593Smuzhiyun #define PCC_IRQ_SOFTWARE1 (IRQ_USER+10) 89*4882a593Smuzhiyun #define PCC_IRQ_SOFTWARE2 (IRQ_USER+11) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define M147_SCC_A_ADDR 0xfffe3002 93*4882a593Smuzhiyun #define M147_SCC_B_ADDR 0xfffe3000 94*4882a593Smuzhiyun #define M147_SCC_PCLK 5000000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45) 97*4882a593Smuzhiyun #define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46) 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* SCC interrupts, for MVME147 */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define MVME147_IRQ_TYPE_PRIO 0 102*4882a593Smuzhiyun #define MVME147_IRQ_SCC_BASE (IRQ_USER+32) 103*4882a593Smuzhiyun #define MVME147_IRQ_SCCB_TX (IRQ_USER+32) 104*4882a593Smuzhiyun #define MVME147_IRQ_SCCB_STAT (IRQ_USER+34) 105*4882a593Smuzhiyun #define MVME147_IRQ_SCCB_RX (IRQ_USER+36) 106*4882a593Smuzhiyun #define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38) 107*4882a593Smuzhiyun #define MVME147_IRQ_SCCA_TX (IRQ_USER+40) 108*4882a593Smuzhiyun #define MVME147_IRQ_SCCA_STAT (IRQ_USER+42) 109*4882a593Smuzhiyun #define MVME147_IRQ_SCCA_RX (IRQ_USER+44) 110*4882a593Smuzhiyun #define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MVME147_LANCE_BASE 0xfffe1800 113*4882a593Smuzhiyun #define MVME147_LANCE_IRQ (IRQ_USER+4) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define ETHERNET_ADDRESS 0xfffe0778 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #endif 118