1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * mcftimer.h -- ColdFire internal TIMER support defines. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 1999-2006, Greg Ungerer <gerg@snapgear.com> 8*4882a593Smuzhiyun * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /****************************************************************************/ 12*4882a593Smuzhiyun #ifndef mcftimer_h 13*4882a593Smuzhiyun #define mcftimer_h 14*4882a593Smuzhiyun /****************************************************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Define the TIMER register set addresses. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ 20*4882a593Smuzhiyun #define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ 21*4882a593Smuzhiyun #define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ 22*4882a593Smuzhiyun #define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ 23*4882a593Smuzhiyun #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x) 24*4882a593Smuzhiyun #define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ 25*4882a593Smuzhiyun #else 26*4882a593Smuzhiyun #define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ 27*4882a593Smuzhiyun #endif 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * Bit definitions for the Timer Mode Register (TMR). 31*4882a593Smuzhiyun * Register bit flags are common across ColdFires. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun #define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ 34*4882a593Smuzhiyun #define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ 35*4882a593Smuzhiyun #define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ 36*4882a593Smuzhiyun #define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ 37*4882a593Smuzhiyun #define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ 38*4882a593Smuzhiyun #define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ 39*4882a593Smuzhiyun #define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ 40*4882a593Smuzhiyun #define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ 41*4882a593Smuzhiyun #define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ 42*4882a593Smuzhiyun #define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ 43*4882a593Smuzhiyun #define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ 44*4882a593Smuzhiyun #define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ 45*4882a593Smuzhiyun #define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ 46*4882a593Smuzhiyun #define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ 47*4882a593Smuzhiyun #define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ 48*4882a593Smuzhiyun #define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ 49*4882a593Smuzhiyun #define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Bit definitions for the Timer Event Registers (TER). 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define MCFTIMER_TER_CAP 0x01 /* Capture event */ 55*4882a593Smuzhiyun #define MCFTIMER_TER_REF 0x02 /* Reference event */ 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /****************************************************************************/ 58*4882a593Smuzhiyun #endif /* mcftimer_h */ 59