1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /****************************************************************************/ 12*4882a593Smuzhiyun #ifndef mcfslt_h 13*4882a593Smuzhiyun #define mcfslt_h 14*4882a593Smuzhiyun /****************************************************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * Define the SLT timer register set addresses. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define MCFSLT_STCNT 0x00 /* Terminal count */ 20*4882a593Smuzhiyun #define MCFSLT_SCR 0x04 /* Control */ 21*4882a593Smuzhiyun #define MCFSLT_SCNT 0x08 /* Current count */ 22*4882a593Smuzhiyun #define MCFSLT_SSR 0x0C /* Status */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Bit definitions for the SCR control register. 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */ 28*4882a593Smuzhiyun #define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */ 29*4882a593Smuzhiyun #define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Bit definitions for the SSR status register. 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */ 35*4882a593Smuzhiyun #define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /****************************************************************************/ 38*4882a593Smuzhiyun #endif /* mcfslt_h */ 39