1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * mcfpit.h -- ColdFire internal PIT timer support defines. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef mcfpit_h 12*4882a593Smuzhiyun #define mcfpit_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Define the PIT timer register address offsets. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun #define MCFPIT_PCSR 0x0 /* PIT control register */ 19*4882a593Smuzhiyun #define MCFPIT_PMR 0x2 /* PIT modulus register */ 20*4882a593Smuzhiyun #define MCFPIT_PCNTR 0x4 /* PIT count register */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Bit definitions for the PIT Control and Status register. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ 26*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ 27*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ 28*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ 29*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ 30*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ 31*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ 32*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ 33*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ 34*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ 35*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ 36*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ 37*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ 38*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ 39*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ 40*4882a593Smuzhiyun #define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ 41*4882a593Smuzhiyun #define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ 42*4882a593Smuzhiyun #define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ 43*4882a593Smuzhiyun #define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ 44*4882a593Smuzhiyun #define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ 45*4882a593Smuzhiyun #define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ 46*4882a593Smuzhiyun #define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ 47*4882a593Smuzhiyun #define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ 48*4882a593Smuzhiyun #define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /****************************************************************************/ 51*4882a593Smuzhiyun #endif /* mcfpit_h */ 52