1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * mcfmmu.h -- definitions for the ColdFire v4e MMU 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 8*4882a593Smuzhiyun * for more details. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef MCFMMU_H 12*4882a593Smuzhiyun #define MCFMMU_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * The MMU support registers are mapped into the address space using 16*4882a593Smuzhiyun * the processor MMUBASE register. We used a fixed address for mapping, 17*4882a593Smuzhiyun * there doesn't seem any need to make this configurable yet. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun #define MMUBASE 0xfe000000 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * The support registers of the MMU. Names are the sames as those 23*4882a593Smuzhiyun * used in the Freescale v4e documentation. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define MMUCR (MMUBASE + 0x00) /* Control register */ 26*4882a593Smuzhiyun #define MMUOR (MMUBASE + 0x04) /* Operation register */ 27*4882a593Smuzhiyun #define MMUSR (MMUBASE + 0x08) /* Status register */ 28*4882a593Smuzhiyun #define MMUAR (MMUBASE + 0x10) /* TLB Address register */ 29*4882a593Smuzhiyun #define MMUTR (MMUBASE + 0x14) /* TLB Tag register */ 30*4882a593Smuzhiyun #define MMUDR (MMUBASE + 0x18) /* TLB Data register */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * MMU Control register bit flags 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun #define MMUCR_EN 0x00000001 /* Virtual mode enable */ 36*4882a593Smuzhiyun #define MMUCR_ASM 0x00000002 /* Address space mode */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * MMU Operation register. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define MMUOR_UAA 0x00000001 /* Update allocation address */ 42*4882a593Smuzhiyun #define MMUOR_ACC 0x00000002 /* TLB access */ 43*4882a593Smuzhiyun #define MMUOR_RD 0x00000004 /* TLB access read */ 44*4882a593Smuzhiyun #define MMUOR_WR 0x00000000 /* TLB access write */ 45*4882a593Smuzhiyun #define MMUOR_ADR 0x00000008 /* TLB address select */ 46*4882a593Smuzhiyun #define MMUOR_ITLB 0x00000010 /* ITLB operation */ 47*4882a593Smuzhiyun #define MMUOR_CAS 0x00000020 /* Clear non-locked ASID TLBs */ 48*4882a593Smuzhiyun #define MMUOR_CNL 0x00000040 /* Clear non-locked TLBs */ 49*4882a593Smuzhiyun #define MMUOR_CA 0x00000080 /* Clear all TLBs */ 50*4882a593Smuzhiyun #define MMUOR_STLB 0x00000100 /* Search TLBs */ 51*4882a593Smuzhiyun #define MMUOR_AAN 16 /* TLB allocation address */ 52*4882a593Smuzhiyun #define MMUOR_AAMASK 0xffff0000 /* AA mask */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * MMU Status register. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun #define MMUSR_HIT 0x00000002 /* Search TLB hit */ 58*4882a593Smuzhiyun #define MMUSR_WF 0x00000008 /* Write access fault */ 59*4882a593Smuzhiyun #define MMUSR_RF 0x00000010 /* Read access fault */ 60*4882a593Smuzhiyun #define MMUSR_SPF 0x00000020 /* Supervisor protect fault */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * MMU Read/Write Tag register. 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define MMUTR_V 0x00000001 /* Valid */ 66*4882a593Smuzhiyun #define MMUTR_SG 0x00000002 /* Shared global */ 67*4882a593Smuzhiyun #define MMUTR_IDN 2 /* Address Space ID */ 68*4882a593Smuzhiyun #define MMUTR_IDMASK 0x000003fc /* ASID mask */ 69*4882a593Smuzhiyun #define MMUTR_VAN 10 /* Virtual Address */ 70*4882a593Smuzhiyun #define MMUTR_VAMASK 0xfffffc00 /* VA mask */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * MMU Read/Write Data register. 74*4882a593Smuzhiyun */ 75*4882a593Smuzhiyun #define MMUDR_LK 0x00000002 /* Lock entry */ 76*4882a593Smuzhiyun #define MMUDR_X 0x00000004 /* Execute access enable */ 77*4882a593Smuzhiyun #define MMUDR_W 0x00000008 /* Write access enable */ 78*4882a593Smuzhiyun #define MMUDR_R 0x00000010 /* Read access enable */ 79*4882a593Smuzhiyun #define MMUDR_SP 0x00000020 /* Supervisor access enable */ 80*4882a593Smuzhiyun #define MMUDR_CM_CWT 0x00000000 /* Cachable write thru */ 81*4882a593Smuzhiyun #define MMUDR_CM_CCB 0x00000040 /* Cachable copy back */ 82*4882a593Smuzhiyun #define MMUDR_CM_NCP 0x00000080 /* Non-cachable precise */ 83*4882a593Smuzhiyun #define MMUDR_CM_NCI 0x000000c0 /* Non-cachable imprecise */ 84*4882a593Smuzhiyun #define MMUDR_SZ_1MB 0x00000000 /* 1MB page size */ 85*4882a593Smuzhiyun #define MMUDR_SZ_4KB 0x00000100 /* 4kB page size */ 86*4882a593Smuzhiyun #define MMUDR_SZ_8KB 0x00000200 /* 8kB page size */ 87*4882a593Smuzhiyun #define MMUDR_SZ_1KB 0x00000300 /* 1kB page size */ 88*4882a593Smuzhiyun #define MMUDR_PAN 10 /* Physical address */ 89*4882a593Smuzhiyun #define MMUDR_PAMASK 0xfffffc00 /* PA mask */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #ifndef __ASSEMBLY__ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * Simple access functions for the MMU registers. Nothing fancy 95*4882a593Smuzhiyun * currently required, just simple 32bit access. 96*4882a593Smuzhiyun */ mmu_read(u32 a)97*4882a593Smuzhiyunstatic inline u32 mmu_read(u32 a) 98*4882a593Smuzhiyun { 99*4882a593Smuzhiyun return *((volatile u32 *) a); 100*4882a593Smuzhiyun } 101*4882a593Smuzhiyun mmu_write(u32 a,u32 v)102*4882a593Smuzhiyunstatic inline void mmu_write(u32 a, u32 v) 103*4882a593Smuzhiyun { 104*4882a593Smuzhiyun *((volatile u32 *) a) = v; 105*4882a593Smuzhiyun __asm__ __volatile__ ("nop"); 106*4882a593Smuzhiyun } 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun void cf_bootmem_alloc(void); 109*4882a593Smuzhiyun void cf_mmu_context_init(void); 110*4882a593Smuzhiyun int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #endif /* MCFMMU_H */ 115