1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun ** macints.h -- Macintosh Linux interrupt handling structs and prototypes 3*4882a593Smuzhiyun ** 4*4882a593Smuzhiyun ** Copyright 1997 by Michael Schmitz 5*4882a593Smuzhiyun ** 6*4882a593Smuzhiyun ** This file is subject to the terms and conditions of the GNU General Public 7*4882a593Smuzhiyun ** License. See the file COPYING in the main directory of this archive 8*4882a593Smuzhiyun ** for more details. 9*4882a593Smuzhiyun ** 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _ASM_MACINTS_H_ 13*4882a593Smuzhiyun #define _ASM_MACINTS_H_ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <asm/irq.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Base IRQ number for all Mac68K interrupt sources. Each source 19*4882a593Smuzhiyun * has eight indexes (base -> base+7). 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define VIA1_SOURCE_BASE 8 23*4882a593Smuzhiyun #define VIA2_SOURCE_BASE 16 24*4882a593Smuzhiyun #define PSC3_SOURCE_BASE 24 25*4882a593Smuzhiyun #define PSC4_SOURCE_BASE 32 26*4882a593Smuzhiyun #define PSC5_SOURCE_BASE 40 27*4882a593Smuzhiyun #define PSC6_SOURCE_BASE 48 28*4882a593Smuzhiyun #define NUBUS_SOURCE_BASE 56 29*4882a593Smuzhiyun #define BABOON_SOURCE_BASE 64 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Maximum IRQ number is BABOON_SOURCE_BASE + 7, 33*4882a593Smuzhiyun * giving us IRQs up through 71 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define NUM_MAC_SOURCES 72 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * clean way to separate IRQ into its source and index 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define IRQ_SRC(irq) (irq >> 3) 43*4882a593Smuzhiyun #define IRQ_IDX(irq) (irq & 7) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* VIA1 interrupts */ 46*4882a593Smuzhiyun #define IRQ_VIA1_0 (8) /* one second int. */ 47*4882a593Smuzhiyun #define IRQ_VIA1_1 (9) /* VBlank int. */ 48*4882a593Smuzhiyun #define IRQ_MAC_VBL IRQ_VIA1_1 49*4882a593Smuzhiyun #define IRQ_VIA1_2 (10) /* ADB SR shifts complete */ 50*4882a593Smuzhiyun #define IRQ_MAC_ADB IRQ_VIA1_2 51*4882a593Smuzhiyun #define IRQ_MAC_ADB_SR IRQ_VIA1_2 52*4882a593Smuzhiyun #define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */ 53*4882a593Smuzhiyun #define IRQ_MAC_ADB_SD IRQ_VIA1_3 54*4882a593Smuzhiyun #define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */ 55*4882a593Smuzhiyun #define IRQ_MAC_ADB_CL IRQ_VIA1_4 56*4882a593Smuzhiyun #define IRQ_VIA1_5 (13) 57*4882a593Smuzhiyun #define IRQ_MAC_TIMER_2 IRQ_VIA1_5 58*4882a593Smuzhiyun #define IRQ_VIA1_6 (14) 59*4882a593Smuzhiyun #define IRQ_MAC_TIMER_1 IRQ_VIA1_6 60*4882a593Smuzhiyun #define IRQ_VIA1_7 (15) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* VIA2/RBV interrupts */ 63*4882a593Smuzhiyun #define IRQ_VIA2_0 (16) 64*4882a593Smuzhiyun #define IRQ_MAC_SCSIDRQ IRQ_VIA2_0 65*4882a593Smuzhiyun #define IRQ_VIA2_1 (17) 66*4882a593Smuzhiyun #define IRQ_MAC_NUBUS IRQ_VIA2_1 67*4882a593Smuzhiyun #define IRQ_VIA2_2 (18) 68*4882a593Smuzhiyun #define IRQ_VIA2_3 (19) 69*4882a593Smuzhiyun #define IRQ_MAC_SCSI IRQ_VIA2_3 70*4882a593Smuzhiyun #define IRQ_VIA2_4 (20) 71*4882a593Smuzhiyun #define IRQ_VIA2_5 (21) 72*4882a593Smuzhiyun #define IRQ_VIA2_6 (22) 73*4882a593Smuzhiyun #define IRQ_VIA2_7 (23) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* Level 3 (PSC, AV Macs only) interrupts */ 76*4882a593Smuzhiyun #define IRQ_PSC3_0 (24) 77*4882a593Smuzhiyun #define IRQ_MAC_MACE IRQ_PSC3_0 78*4882a593Smuzhiyun #define IRQ_PSC3_1 (25) 79*4882a593Smuzhiyun #define IRQ_PSC3_2 (26) 80*4882a593Smuzhiyun #define IRQ_PSC3_3 (27) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Level 4 (PSC, AV Macs only) interrupts */ 83*4882a593Smuzhiyun #define IRQ_PSC4_0 (32) 84*4882a593Smuzhiyun #define IRQ_PSC4_1 (33) 85*4882a593Smuzhiyun #define IRQ_MAC_SCC_A IRQ_PSC4_1 86*4882a593Smuzhiyun #define IRQ_PSC4_2 (34) 87*4882a593Smuzhiyun #define IRQ_MAC_SCC_B IRQ_PSC4_2 88*4882a593Smuzhiyun #define IRQ_PSC4_3 (35) 89*4882a593Smuzhiyun #define IRQ_MAC_MACE_DMA IRQ_PSC4_3 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* OSS Level 4 interrupts */ 92*4882a593Smuzhiyun #define IRQ_MAC_SCC (33) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Level 5 (PSC, AV Macs only) interrupts */ 95*4882a593Smuzhiyun #define IRQ_PSC5_0 (40) 96*4882a593Smuzhiyun #define IRQ_PSC5_1 (41) 97*4882a593Smuzhiyun #define IRQ_PSC5_2 (42) 98*4882a593Smuzhiyun #define IRQ_PSC5_3 (43) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Level 6 (PSC, AV Macs only) interrupts */ 101*4882a593Smuzhiyun #define IRQ_PSC6_0 (48) 102*4882a593Smuzhiyun #define IRQ_PSC6_1 (49) 103*4882a593Smuzhiyun #define IRQ_PSC6_2 (50) 104*4882a593Smuzhiyun #define IRQ_PSC6_3 (51) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* Nubus interrupts (cascaded to VIA2) */ 107*4882a593Smuzhiyun #define IRQ_NUBUS_9 (56) 108*4882a593Smuzhiyun #define IRQ_NUBUS_A (57) 109*4882a593Smuzhiyun #define IRQ_NUBUS_B (58) 110*4882a593Smuzhiyun #define IRQ_NUBUS_C (59) 111*4882a593Smuzhiyun #define IRQ_NUBUS_D (60) 112*4882a593Smuzhiyun #define IRQ_NUBUS_E (61) 113*4882a593Smuzhiyun #define IRQ_NUBUS_F (62) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* Baboon interrupts (cascaded to nubus slot $C) */ 116*4882a593Smuzhiyun #define IRQ_BABOON_0 (64) 117*4882a593Smuzhiyun #define IRQ_BABOON_1 (65) 118*4882a593Smuzhiyun #define IRQ_BABOON_2 (66) 119*4882a593Smuzhiyun #define IRQ_BABOON_3 (67) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define SLOT2IRQ(x) (x + 47) 122*4882a593Smuzhiyun #define IRQ2SLOT(x) (x - 47) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif /* asm/macints.h */ 125