1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef m54xxsim_h 7*4882a593Smuzhiyun #define m54xxsim_h 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m54xx)" 10*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 2 11*4882a593Smuzhiyun #define MCF_BUSCLK (MCF_CLK / 2) 12*4882a593Smuzhiyun #define MACHINE MACH_M54XX 13*4882a593Smuzhiyun #define FPUTYPE FPU_COLDFIRE 14*4882a593Smuzhiyun #define IOMEMBASE MCF_MBAR 15*4882a593Smuzhiyun #define IOMEMSIZE 0x01000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <asm/m54xxacr.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MCFINT_VECBASE 64 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Interrupt Controller Registers 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 27*4882a593Smuzhiyun #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 28*4882a593Smuzhiyun #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 29*4882a593Smuzhiyun #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 30*4882a593Smuzhiyun #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 31*4882a593Smuzhiyun #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 32*4882a593Smuzhiyun #define MCFINTC_IRLR 0x18 /* */ 33*4882a593Smuzhiyun #define MCFINTC_IACKL 0x19 /* */ 34*4882a593Smuzhiyun #define MCFINTC_ICR0 0x40 /* Base ICR register */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * UART module. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */ 40*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */ 41*4882a593Smuzhiyun #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */ 42*4882a593Smuzhiyun #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Define system peripheral IRQ usage. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */ 48*4882a593Smuzhiyun #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */ 49*4882a593Smuzhiyun #define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40) 50*4882a593Smuzhiyun #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35) 51*4882a593Smuzhiyun #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34) 52*4882a593Smuzhiyun #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33) 53*4882a593Smuzhiyun #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Slice Timer support. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */ 59*4882a593Smuzhiyun #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* 62*4882a593Smuzhiyun * Generic GPIO support 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun #define MCFGPIO_PODR (MCF_MBAR + 0xA00) 65*4882a593Smuzhiyun #define MCFGPIO_PDDR (MCF_MBAR + 0xA10) 66*4882a593Smuzhiyun #define MCFGPIO_PPDR (MCF_MBAR + 0xA20) 67*4882a593Smuzhiyun #define MCFGPIO_SETR (MCF_MBAR + 0xA20) 68*4882a593Smuzhiyun #define MCFGPIO_CLRR (MCF_MBAR + 0xA30) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */ 71*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 72*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * EDGE Port support. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */ 78*4882a593Smuzhiyun #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */ 79*4882a593Smuzhiyun #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */ 80*4882a593Smuzhiyun #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */ 81*4882a593Smuzhiyun #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */ 82*4882a593Smuzhiyun #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* 85*4882a593Smuzhiyun * Pin Assignment register definitions 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40) 88*4882a593Smuzhiyun #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42) 89*4882a593Smuzhiyun #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43) 90*4882a593Smuzhiyun #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44) 91*4882a593Smuzhiyun #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */ 92*4882a593Smuzhiyun #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */ 93*4882a593Smuzhiyun #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F) 94*4882a593Smuzhiyun #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E) 95*4882a593Smuzhiyun #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D) 96*4882a593Smuzhiyun #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C) 97*4882a593Smuzhiyun #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50) 98*4882a593Smuzhiyun #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define MCF_PAR_SDA (0x0008) 101*4882a593Smuzhiyun #define MCF_PAR_SCL (0x0004) 102*4882a593Smuzhiyun #define MCF_PAR_PSC_TXD (0x04) 103*4882a593Smuzhiyun #define MCF_PAR_PSC_RXD (0x08) 104*4882a593Smuzhiyun #define MCF_PAR_PSC_CTS_GPIO (0x00) 105*4882a593Smuzhiyun #define MCF_PAR_PSC_CTS_BCLK (0x80) 106*4882a593Smuzhiyun #define MCF_PAR_PSC_CTS_CTS (0xC0) 107*4882a593Smuzhiyun #define MCF_PAR_PSC_RTS_GPIO (0x00) 108*4882a593Smuzhiyun #define MCF_PAR_PSC_RTS_FSYNC (0x20) 109*4882a593Smuzhiyun #define MCF_PAR_PSC_RTS_RTS (0x30) 110*4882a593Smuzhiyun #define MCF_PAR_PSC_CANRX (0x40) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */ 113*4882a593Smuzhiyun #define MCF_PAR_FECI2CIRQ_SDA (1 << 3) 114*4882a593Smuzhiyun #define MCF_PAR_FECI2CIRQ_SCL (1 << 2) 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* 117*4882a593Smuzhiyun * I2C module. 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun #define MCFI2C_BASE0 (MCF_MBAR + 0x8f00) 120*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #endif /* m54xxsim_h */ 123