1*4882a593Smuzhiyun /****************************************************************************/ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun /* 4*4882a593Smuzhiyun * m54xxpci.h -- ColdFire 547x and 548x PCI bus support 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public 9*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive 10*4882a593Smuzhiyun * for more details. 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun #ifndef M54XXPCI_H 15*4882a593Smuzhiyun #define M54XXPCI_H 16*4882a593Smuzhiyun /****************************************************************************/ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * The core set of PCI support registers are mapped into the MBAR region. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */ 22*4882a593Smuzhiyun #define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */ 23*4882a593Smuzhiyun #define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */ 24*4882a593Smuzhiyun #define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */ 25*4882a593Smuzhiyun #define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */ 26*4882a593Smuzhiyun #define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */ 27*4882a593Smuzhiyun #define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */ 28*4882a593Smuzhiyun #define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */ 29*4882a593Smuzhiyun #define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */ 30*4882a593Smuzhiyun #define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */ 31*4882a593Smuzhiyun #define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */ 34*4882a593Smuzhiyun #define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */ 35*4882a593Smuzhiyun #define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */ 36*4882a593Smuzhiyun #define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */ 37*4882a593Smuzhiyun #define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */ 38*4882a593Smuzhiyun #define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */ 39*4882a593Smuzhiyun #define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */ 40*4882a593Smuzhiyun #define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */ 41*4882a593Smuzhiyun #define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */ 42*4882a593Smuzhiyun #define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */ 43*4882a593Smuzhiyun #define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */ 46*4882a593Smuzhiyun #define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */ 47*4882a593Smuzhiyun #define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */ 48*4882a593Smuzhiyun #define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */ 49*4882a593Smuzhiyun #define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */ 50*4882a593Smuzhiyun #define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */ 51*4882a593Smuzhiyun #define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */ 52*4882a593Smuzhiyun #define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */ 53*4882a593Smuzhiyun #define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */ 54*4882a593Smuzhiyun #define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */ 55*4882a593Smuzhiyun #define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */ 56*4882a593Smuzhiyun #define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */ 57*4882a593Smuzhiyun #define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */ 58*4882a593Smuzhiyun #define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */ 61*4882a593Smuzhiyun #define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */ 62*4882a593Smuzhiyun #define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */ 63*4882a593Smuzhiyun #define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */ 64*4882a593Smuzhiyun #define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */ 65*4882a593Smuzhiyun #define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */ 66*4882a593Smuzhiyun #define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */ 67*4882a593Smuzhiyun #define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */ 68*4882a593Smuzhiyun #define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */ 69*4882a593Smuzhiyun #define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */ 70*4882a593Smuzhiyun #define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */ 71*4882a593Smuzhiyun #define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */ 72*4882a593Smuzhiyun #define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */ 75*4882a593Smuzhiyun #define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* 78*4882a593Smuzhiyun * Definitions for the Global status and control register. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun #define PCIGSCR_PE 0x20000000 /* Parity error detected */ 81*4882a593Smuzhiyun #define PCIGSCR_SE 0x10000000 /* System error detected */ 82*4882a593Smuzhiyun #define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */ 83*4882a593Smuzhiyun #define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */ 84*4882a593Smuzhiyun #define PCIGSCR_SEE 0x00001000 /* System error intr enable */ 85*4882a593Smuzhiyun #define PCIGSCR_RESET 0x00000001 /* Reset bit */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * Bit definitions for the PCICAR configuration address register. 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #define PCICAR_E 0x80000000 /* Enable config space */ 91*4882a593Smuzhiyun #define PCICAR_BUSN 16 /* Move bus bits */ 92*4882a593Smuzhiyun #define PCICAR_DEVFNN 8 /* Move devfn bits */ 93*4882a593Smuzhiyun #define PCICAR_DWORDN 0 /* Move dword bits */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * The initiator windows hold the memory and IO mapping information. 97*4882a593Smuzhiyun * This macro creates the register values from the desired addresses. 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun #define WXBTAR(hostaddr, pciaddr, size) \ 100*4882a593Smuzhiyun (((hostaddr) & 0xff000000) | \ 101*4882a593Smuzhiyun ((((size) - 1) & 0xff000000) >> 8) | \ 102*4882a593Smuzhiyun (((pciaddr) & 0xff000000) >> 16)) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */ 105*4882a593Smuzhiyun #define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */ 106*4882a593Smuzhiyun #define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */ 107*4882a593Smuzhiyun #define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */ 108*4882a593Smuzhiyun #define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */ 109*4882a593Smuzhiyun #define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */ 112*4882a593Smuzhiyun #define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */ 113*4882a593Smuzhiyun #define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */ 114*4882a593Smuzhiyun #define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */ 115*4882a593Smuzhiyun #define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */ 116*4882a593Smuzhiyun #define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* 119*4882a593Smuzhiyun * Bit definitions for the PCIBATR registers. 120*4882a593Smuzhiyun */ 121*4882a593Smuzhiyun #define PCITBATR0_E 0x00000001 /* Enable window 0 */ 122*4882a593Smuzhiyun #define PCITBATR1_E 0x00000001 /* Enable window 1 */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * PCI arbiter support definitions and macros. 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun #define PACR_INTMPRI 0x00000001 128*4882a593Smuzhiyun #define PACR_EXTMPRI(x) (((x) & 0x1f) << 1) 129*4882a593Smuzhiyun #define PACR_INTMINTE 0x00010000 130*4882a593Smuzhiyun #define PACR_EXTMINTE(x) (((x) & 0x1f) << 17) 131*4882a593Smuzhiyun #define PACR_PKMD 0x40000000 132*4882a593Smuzhiyun #define PACR_DS 0x80000000 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */ 135*4882a593Smuzhiyun #define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /****************************************************************************/ 138*4882a593Smuzhiyun #endif /* M54XXPCI_H */ 139