xref: /OK3568_Linux_fs/kernel/arch/m68k/include/asm/m54xxgpt.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * File:	m54xxgpt.h
4*4882a593Smuzhiyun  * Purpose:	Register and bit definitions for the MCF54XX
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Notes:
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #ifndef m54xxgpt_h
11*4882a593Smuzhiyun #define m54xxgpt_h
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*********************************************************************
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * General Purpose Timers (GPT)
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun *********************************************************************/
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* Register read/write macros */
20*4882a593Smuzhiyun #define MCF_GPT_GMS0       (MCF_MBAR + 0x000800)
21*4882a593Smuzhiyun #define MCF_GPT_GCIR0      (MCF_MBAR + 0x000804)
22*4882a593Smuzhiyun #define MCF_GPT_GPWM0      (MCF_MBAR + 0x000808)
23*4882a593Smuzhiyun #define MCF_GPT_GSR0       (MCF_MBAR + 0x00080C)
24*4882a593Smuzhiyun #define MCF_GPT_GMS1       (MCF_MBAR + 0x000810)
25*4882a593Smuzhiyun #define MCF_GPT_GCIR1      (MCF_MBAR + 0x000814)
26*4882a593Smuzhiyun #define MCF_GPT_GPWM1      (MCF_MBAR + 0x000818)
27*4882a593Smuzhiyun #define MCF_GPT_GSR1       (MCF_MBAR + 0x00081C)
28*4882a593Smuzhiyun #define MCF_GPT_GMS2       (MCF_MBAR + 0x000820)
29*4882a593Smuzhiyun #define MCF_GPT_GCIR2      (MCF_MBAR + 0x000824)
30*4882a593Smuzhiyun #define MCF_GPT_GPWM2      (MCF_MBAR + 0x000828)
31*4882a593Smuzhiyun #define MCF_GPT_GSR2       (MCF_MBAR + 0x00082C)
32*4882a593Smuzhiyun #define MCF_GPT_GMS3       (MCF_MBAR + 0x000830)
33*4882a593Smuzhiyun #define MCF_GPT_GCIR3      (MCF_MBAR + 0x000834)
34*4882a593Smuzhiyun #define MCF_GPT_GPWM3      (MCF_MBAR + 0x000838)
35*4882a593Smuzhiyun #define MCF_GPT_GSR3       (MCF_MBAR + 0x00083C)
36*4882a593Smuzhiyun #define MCF_GPT_GMS(x)     (MCF_MBAR + 0x000800 + ((x) * 0x010))
37*4882a593Smuzhiyun #define MCF_GPT_GCIR(x)    (MCF_MBAR + 0x000804 + ((x) * 0x010))
38*4882a593Smuzhiyun #define MCF_GPT_GPWM(x)    (MCF_MBAR + 0x000808 + ((x) * 0x010))
39*4882a593Smuzhiyun #define MCF_GPT_GSR(x)     (MCF_MBAR + 0x00080C + ((x) * 0x010))
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /* Bit definitions and macros for MCF_GPT_GMS */
42*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS(x)         (((x)&0x00000007)<<0)
43*4882a593Smuzhiyun #define MCF_GPT_GMS_GPIO(x)        (((x)&0x00000003)<<4)
44*4882a593Smuzhiyun #define MCF_GPT_GMS_IEN            (0x00000100)
45*4882a593Smuzhiyun #define MCF_GPT_GMS_OD             (0x00000200)
46*4882a593Smuzhiyun #define MCF_GPT_GMS_SC             (0x00000400)
47*4882a593Smuzhiyun #define MCF_GPT_GMS_CE             (0x00001000)
48*4882a593Smuzhiyun #define MCF_GPT_GMS_WDEN           (0x00008000)
49*4882a593Smuzhiyun #define MCF_GPT_GMS_ICT(x)         (((x)&0x00000003)<<16)
50*4882a593Smuzhiyun #define MCF_GPT_GMS_OCT(x)         (((x)&0x00000003)<<20)
51*4882a593Smuzhiyun #define MCF_GPT_GMS_OCPW(x)        (((x)&0x000000FF)<<24)
52*4882a593Smuzhiyun #define MCF_GPT_GMS_OCT_FRCLOW     (0x00000000)
53*4882a593Smuzhiyun #define MCF_GPT_GMS_OCT_PULSEHI    (0x00100000)
54*4882a593Smuzhiyun #define MCF_GPT_GMS_OCT_PULSELO    (0x00200000)
55*4882a593Smuzhiyun #define MCF_GPT_GMS_OCT_TOGGLE     (0x00300000)
56*4882a593Smuzhiyun #define MCF_GPT_GMS_ICT_ANY        (0x00000000)
57*4882a593Smuzhiyun #define MCF_GPT_GMS_ICT_RISE       (0x00010000)
58*4882a593Smuzhiyun #define MCF_GPT_GMS_ICT_FALL       (0x00020000)
59*4882a593Smuzhiyun #define MCF_GPT_GMS_ICT_PULSE      (0x00030000)
60*4882a593Smuzhiyun #define MCF_GPT_GMS_GPIO_INPUT     (0x00000000)
61*4882a593Smuzhiyun #define MCF_GPT_GMS_GPIO_OUTLO     (0x00000020)
62*4882a593Smuzhiyun #define MCF_GPT_GMS_GPIO_OUTHI     (0x00000030)
63*4882a593Smuzhiyun #define MCF_GPT_GMS_GPIO_MASK      (0x00000030)
64*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_DISABLE    (0x00000000)
65*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_INCAPT     (0x00000001)
66*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_OUTCAPT    (0x00000002)
67*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_PWM        (0x00000003)
68*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_GPIO       (0x00000004)
69*4882a593Smuzhiyun #define MCF_GPT_GMS_TMS_MASK       (0x00000007)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* Bit definitions and macros for MCF_GPT_GCIR */
72*4882a593Smuzhiyun #define MCF_GPT_GCIR_CNT(x)        (((x)&0x0000FFFF)<<0)
73*4882a593Smuzhiyun #define MCF_GPT_GCIR_PRE(x)        (((x)&0x0000FFFF)<<16)
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun /* Bit definitions and macros for MCF_GPT_GPWM */
76*4882a593Smuzhiyun #define MCF_GPT_GPWM_LOAD          (0x00000001)
77*4882a593Smuzhiyun #define MCF_GPT_GPWM_PWMOP         (0x00000100)
78*4882a593Smuzhiyun #define MCF_GPT_GPWM_WIDTH(x)      (((x)&0x0000FFFF)<<16)
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun /* Bit definitions and macros for MCF_GPT_GSR */
81*4882a593Smuzhiyun #define MCF_GPT_GSR_CAPT           (0x00000001)
82*4882a593Smuzhiyun #define MCF_GPT_GSR_COMP           (0x00000002)
83*4882a593Smuzhiyun #define MCF_GPT_GSR_PWMP           (0x00000004)
84*4882a593Smuzhiyun #define MCF_GPT_GSR_TEXP           (0x00000008)
85*4882a593Smuzhiyun #define MCF_GPT_GSR_PIN            (0x00000100)
86*4882a593Smuzhiyun #define MCF_GPT_GSR_OVF(x)         (((x)&0x00000007)<<12)
87*4882a593Smuzhiyun #define MCF_GPT_GSR_CAPTURE(x)     (((x)&0x0000FFFF)<<16)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /********************************************************************/
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #endif /* m54xxgpt_h */
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