1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m52xxacr.h -- ColdFire version 2 core cache support 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef m52xxacr_h 12*4882a593Smuzhiyun #define m52xxacr_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * All varients of the ColdFire using version 2 cores have a similar 17*4882a593Smuzhiyun * cache setup. Although not absolutely identical the cache register 18*4882a593Smuzhiyun * definitions are compatible for all of them. Mostly they support a 19*4882a593Smuzhiyun * configurable cache memory that can be instruction only, data only, 20*4882a593Smuzhiyun * or split instruction and data. The exception is the very old version 2 21*4882a593Smuzhiyun * core based parts, like the 5206(e), 5249 and 5272, which are instruction 22*4882a593Smuzhiyun * cache only. Cache size varies from 2k up to 16k. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * Define the Cache Control register flags. 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define CACR_CENB 0x80000000 /* Enable cache */ 29*4882a593Smuzhiyun #define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */ 30*4882a593Smuzhiyun #define CACR_CFRZ 0x08000000 /* Cache freeze mode */ 31*4882a593Smuzhiyun #define CACR_CINV 0x01000000 /* Invalidate cache */ 32*4882a593Smuzhiyun #define CACR_DISI 0x00800000 /* Disable instruction cache */ 33*4882a593Smuzhiyun #define CACR_DISD 0x00400000 /* Disable data cache */ 34*4882a593Smuzhiyun #define CACR_INVI 0x00200000 /* Invalidate instruction cache */ 35*4882a593Smuzhiyun #define CACR_INVD 0x00100000 /* Invalidate data cache */ 36*4882a593Smuzhiyun #define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */ 37*4882a593Smuzhiyun #define CACR_DCM 0x00000200 /* Default cache mode */ 38*4882a593Smuzhiyun #define CACR_DBWE 0x00000100 /* Buffered write enable */ 39*4882a593Smuzhiyun #define CACR_DWP 0x00000020 /* Write protection */ 40*4882a593Smuzhiyun #define CACR_EUSP 0x00000010 /* Enable separate user a7 */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * Define the Access Control register flags. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ 46*4882a593Smuzhiyun #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ 47*4882a593Smuzhiyun #define ACR_ENABLE 0x00008000 /* Enable this ACR */ 48*4882a593Smuzhiyun #define ACR_USER 0x00000000 /* Allow only user accesses */ 49*4882a593Smuzhiyun #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ 50*4882a593Smuzhiyun #define ACR_ANY 0x00004000 /* Allow any access type */ 51*4882a593Smuzhiyun #define ACR_CENB 0x00000000 /* Caching of region enabled */ 52*4882a593Smuzhiyun #define ACR_CDIS 0x00000040 /* Caching of region disabled */ 53*4882a593Smuzhiyun #define ACR_BWE 0x00000020 /* Write buffer enabled */ 54*4882a593Smuzhiyun #define ACR_WPROTECT 0x00000004 /* Write protect region */ 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * Set the cache controller settings we will use. On the cores that support 58*4882a593Smuzhiyun * a split cache configuration we allow all the combinations at Kconfig 59*4882a593Smuzhiyun * time. For those cores that only have an instruction cache we just set 60*4882a593Smuzhiyun * that as on. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #if defined(CONFIG_CACHE_I) 63*4882a593Smuzhiyun #define CACHE_TYPE (CACR_DISD + CACR_EUSP) 64*4882a593Smuzhiyun #define CACHE_INVTYPEI 0 65*4882a593Smuzhiyun #elif defined(CONFIG_CACHE_D) 66*4882a593Smuzhiyun #define CACHE_TYPE (CACR_DISI + CACR_EUSP) 67*4882a593Smuzhiyun #define CACHE_INVTYPED 0 68*4882a593Smuzhiyun #elif defined(CONFIG_CACHE_BOTH) 69*4882a593Smuzhiyun #define CACHE_TYPE CACR_EUSP 70*4882a593Smuzhiyun #define CACHE_INVTYPEI CACR_INVI 71*4882a593Smuzhiyun #define CACHE_INVTYPED CACR_INVD 72*4882a593Smuzhiyun #else 73*4882a593Smuzhiyun /* This is the instruction cache only devices (no split cache, no eusp) */ 74*4882a593Smuzhiyun #define CACHE_TYPE 0 75*4882a593Smuzhiyun #define CACHE_INVTYPEI 0 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define CACHE_INIT (CACR_CINV + CACHE_TYPE) 79*4882a593Smuzhiyun #define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV) 82*4882a593Smuzhiyun #if defined(CACHE_INVTYPEI) 83*4882a593Smuzhiyun #define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI) 84*4882a593Smuzhiyun #endif 85*4882a593Smuzhiyun #if defined(CACHE_INVTYPED) 86*4882a593Smuzhiyun #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED) 87*4882a593Smuzhiyun #endif 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 90*4882a593Smuzhiyun (0x000f0000) + \ 91*4882a593Smuzhiyun (ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE)) 92*4882a593Smuzhiyun #define ACR1_MODE 0 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /****************************************************************************/ 95*4882a593Smuzhiyun #endif /* m52xxsim_h */ 96