1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m5272sim.h -- ColdFire 5272 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) 8*4882a593Smuzhiyun * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /****************************************************************************/ 12*4882a593Smuzhiyun #ifndef m5272sim_h 13*4882a593Smuzhiyun #define m5272sim_h 14*4882a593Smuzhiyun /****************************************************************************/ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m5272)" 17*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 18*4882a593Smuzhiyun #define MCF_BUSCLK MCF_CLK 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include <asm/m52xxacr.h> 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Define the 5272 SIM register set addresses. 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define MCFSIM_SCR (MCF_MBAR + 0x04) /* SIM Config reg */ 26*4882a593Smuzhiyun #define MCFSIM_SPR (MCF_MBAR + 0x06) /* System Protection */ 27*4882a593Smuzhiyun #define MCFSIM_PMR (MCF_MBAR + 0x08) /* Power Management */ 28*4882a593Smuzhiyun #define MCFSIM_APMR (MCF_MBAR + 0x0e) /* Active Low Power */ 29*4882a593Smuzhiyun #define MCFSIM_DIR (MCF_MBAR + 0x10) /* Device Identity */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define MCFSIM_ICR1 (MCF_MBAR + 0x20) /* Intr Ctrl reg 1 */ 32*4882a593Smuzhiyun #define MCFSIM_ICR2 (MCF_MBAR + 0x24) /* Intr Ctrl reg 2 */ 33*4882a593Smuzhiyun #define MCFSIM_ICR3 (MCF_MBAR + 0x28) /* Intr Ctrl reg 3 */ 34*4882a593Smuzhiyun #define MCFSIM_ICR4 (MCF_MBAR + 0x2c) /* Intr Ctrl reg 4 */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define MCFSIM_ISR (MCF_MBAR + 0x30) /* Intr Source */ 37*4882a593Smuzhiyun #define MCFSIM_PITR (MCF_MBAR + 0x34) /* Intr Transition */ 38*4882a593Smuzhiyun #define MCFSIM_PIWR (MCF_MBAR + 0x38) /* Intr Wakeup */ 39*4882a593Smuzhiyun #define MCFSIM_PIVR (MCF_MBAR + 0x3f) /* Intr Vector */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define MCFSIM_WRRR (MCF_MBAR + 0x280) /* Watchdog reference */ 42*4882a593Smuzhiyun #define MCFSIM_WIRR (MCF_MBAR + 0x284) /* Watchdog interrupt */ 43*4882a593Smuzhiyun #define MCFSIM_WCR (MCF_MBAR + 0x288) /* Watchdog counter */ 44*4882a593Smuzhiyun #define MCFSIM_WER (MCF_MBAR + 0x28c) /* Watchdog event */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define MCFSIM_CSBR0 (MCF_MBAR + 0x40) /* CS0 Base Address */ 47*4882a593Smuzhiyun #define MCFSIM_CSOR0 (MCF_MBAR + 0x44) /* CS0 Option */ 48*4882a593Smuzhiyun #define MCFSIM_CSBR1 (MCF_MBAR + 0x48) /* CS1 Base Address */ 49*4882a593Smuzhiyun #define MCFSIM_CSOR1 (MCF_MBAR + 0x4c) /* CS1 Option */ 50*4882a593Smuzhiyun #define MCFSIM_CSBR2 (MCF_MBAR + 0x50) /* CS2 Base Address */ 51*4882a593Smuzhiyun #define MCFSIM_CSOR2 (MCF_MBAR + 0x54) /* CS2 Option */ 52*4882a593Smuzhiyun #define MCFSIM_CSBR3 (MCF_MBAR + 0x58) /* CS3 Base Address */ 53*4882a593Smuzhiyun #define MCFSIM_CSOR3 (MCF_MBAR + 0x5c) /* CS3 Option */ 54*4882a593Smuzhiyun #define MCFSIM_CSBR4 (MCF_MBAR + 0x60) /* CS4 Base Address */ 55*4882a593Smuzhiyun #define MCFSIM_CSOR4 (MCF_MBAR + 0x64) /* CS4 Option */ 56*4882a593Smuzhiyun #define MCFSIM_CSBR5 (MCF_MBAR + 0x68) /* CS5 Base Address */ 57*4882a593Smuzhiyun #define MCFSIM_CSOR5 (MCF_MBAR + 0x6c) /* CS5 Option */ 58*4882a593Smuzhiyun #define MCFSIM_CSBR6 (MCF_MBAR + 0x70) /* CS6 Base Address */ 59*4882a593Smuzhiyun #define MCFSIM_CSOR6 (MCF_MBAR + 0x74) /* CS6 Option */ 60*4882a593Smuzhiyun #define MCFSIM_CSBR7 (MCF_MBAR + 0x78) /* CS7 Base Address */ 61*4882a593Smuzhiyun #define MCFSIM_CSOR7 (MCF_MBAR + 0x7c) /* CS7 Option */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define MCFSIM_SDCR (MCF_MBAR + 0x180) /* SDRAM Config */ 64*4882a593Smuzhiyun #define MCFSIM_SDTR (MCF_MBAR + 0x184) /* SDRAM Timing */ 65*4882a593Smuzhiyun #define MCFSIM_DCAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address */ 66*4882a593Smuzhiyun #define MCFSIM_DCMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask */ 67*4882a593Smuzhiyun #define MCFSIM_DCCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control */ 68*4882a593Smuzhiyun #define MCFSIM_DCAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address */ 69*4882a593Smuzhiyun #define MCFSIM_DCMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg */ 70*4882a593Smuzhiyun #define MCFSIM_DCCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MCFUART_BASE0 (MCF_MBAR + 0x100) /* Base address UART0 */ 73*4882a593Smuzhiyun #define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */ 76*4882a593Smuzhiyun #define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */ 77*4882a593Smuzhiyun #define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */ 78*4882a593Smuzhiyun #define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */ 79*4882a593Smuzhiyun #define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */ 80*4882a593Smuzhiyun #define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */ 81*4882a593Smuzhiyun #define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */ 82*4882a593Smuzhiyun #define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */ 83*4882a593Smuzhiyun #define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #define MCFDMA_BASE0 (MCF_MBAR + 0xe0) /* Base address DMA 0 */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MCFTIMER_BASE1 (MCF_MBAR + 0x200) /* Base address TIMER1 */ 88*4882a593Smuzhiyun #define MCFTIMER_BASE2 (MCF_MBAR + 0x220) /* Base address TIMER2 */ 89*4882a593Smuzhiyun #define MCFTIMER_BASE3 (MCF_MBAR + 0x240) /* Base address TIMER4 */ 90*4882a593Smuzhiyun #define MCFTIMER_BASE4 (MCF_MBAR + 0x260) /* Base address TIMER3 */ 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define MCFFEC_BASE0 (MCF_MBAR + 0x840) /* Base FEC ethernet */ 93*4882a593Smuzhiyun #define MCFFEC_SIZE0 0x1d0 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * Define system peripheral IRQ usage. 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun #define MCFINT_VECBASE 64 /* Base of interrupts */ 99*4882a593Smuzhiyun #define MCF_IRQ_SPURIOUS 64 /* User Spurious */ 100*4882a593Smuzhiyun #define MCF_IRQ_EINT1 65 /* External Interrupt 1 */ 101*4882a593Smuzhiyun #define MCF_IRQ_EINT2 66 /* External Interrupt 2 */ 102*4882a593Smuzhiyun #define MCF_IRQ_EINT3 67 /* External Interrupt 3 */ 103*4882a593Smuzhiyun #define MCF_IRQ_EINT4 68 /* External Interrupt 4 */ 104*4882a593Smuzhiyun #define MCF_IRQ_TIMER1 69 /* Timer 1 */ 105*4882a593Smuzhiyun #define MCF_IRQ_TIMER2 70 /* Timer 2 */ 106*4882a593Smuzhiyun #define MCF_IRQ_TIMER3 71 /* Timer 3 */ 107*4882a593Smuzhiyun #define MCF_IRQ_TIMER4 72 /* Timer 4 */ 108*4882a593Smuzhiyun #define MCF_IRQ_UART0 73 /* UART 0 */ 109*4882a593Smuzhiyun #define MCF_IRQ_UART1 74 /* UART 1 */ 110*4882a593Smuzhiyun #define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */ 111*4882a593Smuzhiyun #define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */ 112*4882a593Smuzhiyun #define MCF_IRQ_USB0 77 /* USB Endpoint 0 */ 113*4882a593Smuzhiyun #define MCF_IRQ_USB1 78 /* USB Endpoint 1 */ 114*4882a593Smuzhiyun #define MCF_IRQ_USB2 79 /* USB Endpoint 2 */ 115*4882a593Smuzhiyun #define MCF_IRQ_USB3 80 /* USB Endpoint 3 */ 116*4882a593Smuzhiyun #define MCF_IRQ_USB4 81 /* USB Endpoint 4 */ 117*4882a593Smuzhiyun #define MCF_IRQ_USB5 82 /* USB Endpoint 5 */ 118*4882a593Smuzhiyun #define MCF_IRQ_USB6 83 /* USB Endpoint 6 */ 119*4882a593Smuzhiyun #define MCF_IRQ_USB7 84 /* USB Endpoint 7 */ 120*4882a593Smuzhiyun #define MCF_IRQ_DMA 85 /* DMA Controller */ 121*4882a593Smuzhiyun #define MCF_IRQ_FECRX0 86 /* Ethernet Receiver */ 122*4882a593Smuzhiyun #define MCF_IRQ_FECTX0 87 /* Ethernet Transmitter */ 123*4882a593Smuzhiyun #define MCF_IRQ_FECENTC0 88 /* Ethernet Non-Time Critical */ 124*4882a593Smuzhiyun #define MCF_IRQ_QSPI 89 /* Queued Serial Interface */ 125*4882a593Smuzhiyun #define MCF_IRQ_EINT5 90 /* External Interrupt 5 */ 126*4882a593Smuzhiyun #define MCF_IRQ_EINT6 91 /* External Interrupt 6 */ 127*4882a593Smuzhiyun #define MCF_IRQ_SWTO 92 /* Software Watchdog */ 128*4882a593Smuzhiyun #define MCFINT_VECMAX 95 /* Maxmum interrupt */ 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define MCF_IRQ_TIMER MCF_IRQ_TIMER1 131*4882a593Smuzhiyun #define MCF_IRQ_PROFILER MCF_IRQ_TIMER2 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* 134*4882a593Smuzhiyun * Generic GPIO support 135*4882a593Smuzhiyun */ 136*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 48 137*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX -1 138*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE -1 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /****************************************************************************/ 141*4882a593Smuzhiyun #endif /* m5272sim_h */ 142