1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /****************************************************************************/ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* 5*4882a593Smuzhiyun * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /****************************************************************************/ 11*4882a593Smuzhiyun #ifndef m520xsim_h 12*4882a593Smuzhiyun #define m520xsim_h 13*4882a593Smuzhiyun /****************************************************************************/ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define CPU_NAME "COLDFIRE(m520x)" 16*4882a593Smuzhiyun #define CPU_INSTR_PER_JIFFY 3 17*4882a593Smuzhiyun #define MCF_BUSCLK (MCF_CLK / 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #include <asm/m52xxacr.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Define the 520x SIM register set addresses. 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun #define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */ 25*4882a593Smuzhiyun #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 26*4882a593Smuzhiyun #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 27*4882a593Smuzhiyun #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 28*4882a593Smuzhiyun #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 29*4882a593Smuzhiyun #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 30*4882a593Smuzhiyun #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 31*4882a593Smuzhiyun #define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */ 32*4882a593Smuzhiyun #define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */ 33*4882a593Smuzhiyun #define MCFINTC_ICR0 0x40 /* Base ICR register */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 36*4882a593Smuzhiyun * The common interrupt controller code just wants to know the absolute 37*4882a593Smuzhiyun * address to the SIMR and CIMR registers (not offsets into IPSBAR). 38*4882a593Smuzhiyun * The 520x family only has a single INTC unit. 39*4882a593Smuzhiyun */ 40*4882a593Smuzhiyun #define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR) 41*4882a593Smuzhiyun #define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR) 42*4882a593Smuzhiyun #define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0) 43*4882a593Smuzhiyun #define MCFINTC1_SIMR (0) 44*4882a593Smuzhiyun #define MCFINTC1_CIMR (0) 45*4882a593Smuzhiyun #define MCFINTC1_ICR0 (0) 46*4882a593Smuzhiyun #define MCFINTC2_SIMR (0) 47*4882a593Smuzhiyun #define MCFINTC2_CIMR (0) 48*4882a593Smuzhiyun #define MCFINTC2_ICR0 (0) 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define MCFINT_VECBASE 64 51*4882a593Smuzhiyun #define MCFINT_UART0 26 /* Interrupt number for UART0 */ 52*4882a593Smuzhiyun #define MCFINT_UART1 27 /* Interrupt number for UART1 */ 53*4882a593Smuzhiyun #define MCFINT_UART2 28 /* Interrupt number for UART2 */ 54*4882a593Smuzhiyun #define MCFINT_I2C0 30 /* Interrupt number for I2C */ 55*4882a593Smuzhiyun #define MCFINT_QSPI 31 /* Interrupt number for QSPI */ 56*4882a593Smuzhiyun #define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */ 57*4882a593Smuzhiyun #define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */ 58*4882a593Smuzhiyun #define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */ 59*4882a593Smuzhiyun #define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 62*4882a593Smuzhiyun #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 63*4882a593Smuzhiyun #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 66*4882a593Smuzhiyun #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 67*4882a593Smuzhiyun #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 70*4882a593Smuzhiyun #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * SDRAM configuration registers. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */ 77*4882a593Smuzhiyun #define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */ 78*4882a593Smuzhiyun #define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */ 79*4882a593Smuzhiyun #define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */ 80*4882a593Smuzhiyun #define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */ 81*4882a593Smuzhiyun #define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * EPORT and GPIO registers. 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun #define MCFEPORT_EPPAR 0xFC088000 87*4882a593Smuzhiyun #define MCFEPORT_EPDDR 0xFC088002 88*4882a593Smuzhiyun #define MCFEPORT_EPIER 0xFC088003 89*4882a593Smuzhiyun #define MCFEPORT_EPDR 0xFC088004 90*4882a593Smuzhiyun #define MCFEPORT_EPPDR 0xFC088005 91*4882a593Smuzhiyun #define MCFEPORT_EPFR 0xFC088006 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define MCFGPIO_PODR_BUSCTL 0xFC0A4000 94*4882a593Smuzhiyun #define MCFGPIO_PODR_BE 0xFC0A4001 95*4882a593Smuzhiyun #define MCFGPIO_PODR_CS 0xFC0A4002 96*4882a593Smuzhiyun #define MCFGPIO_PODR_FECI2C 0xFC0A4003 97*4882a593Smuzhiyun #define MCFGPIO_PODR_QSPI 0xFC0A4004 98*4882a593Smuzhiyun #define MCFGPIO_PODR_TIMER 0xFC0A4005 99*4882a593Smuzhiyun #define MCFGPIO_PODR_UART 0xFC0A4006 100*4882a593Smuzhiyun #define MCFGPIO_PODR_FECH 0xFC0A4007 101*4882a593Smuzhiyun #define MCFGPIO_PODR_FECL 0xFC0A4008 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define MCFGPIO_PDDR_BUSCTL 0xFC0A400C 104*4882a593Smuzhiyun #define MCFGPIO_PDDR_BE 0xFC0A400D 105*4882a593Smuzhiyun #define MCFGPIO_PDDR_CS 0xFC0A400E 106*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECI2C 0xFC0A400F 107*4882a593Smuzhiyun #define MCFGPIO_PDDR_QSPI 0xFC0A4010 108*4882a593Smuzhiyun #define MCFGPIO_PDDR_TIMER 0xFC0A4011 109*4882a593Smuzhiyun #define MCFGPIO_PDDR_UART 0xFC0A4012 110*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECH 0xFC0A4013 111*4882a593Smuzhiyun #define MCFGPIO_PDDR_FECL 0xFC0A4014 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_CS 0xFC0A401A 114*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B 115*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_QSPI 0xFC0A401C 116*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_TIMER 0xFC0A401D 117*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_UART 0xFC0A401E 118*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECH 0xFC0A401F 119*4882a593Smuzhiyun #define MCFGPIO_PPDSDR_FECL 0xFC0A4020 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 122*4882a593Smuzhiyun #define MCFGPIO_PCLRR_BE 0xFC0A4025 123*4882a593Smuzhiyun #define MCFGPIO_PCLRR_CS 0xFC0A4026 124*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECI2C 0xFC0A4027 125*4882a593Smuzhiyun #define MCFGPIO_PCLRR_QSPI 0xFC0A4028 126*4882a593Smuzhiyun #define MCFGPIO_PCLRR_TIMER 0xFC0A4029 127*4882a593Smuzhiyun #define MCFGPIO_PCLRR_UART 0xFC0A402A 128*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECH 0xFC0A402B 129*4882a593Smuzhiyun #define MCFGPIO_PCLRR_FECL 0xFC0A402C 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* 132*4882a593Smuzhiyun * Generic GPIO support 133*4882a593Smuzhiyun */ 134*4882a593Smuzhiyun #define MCFGPIO_PODR MCFGPIO_PODR_CS 135*4882a593Smuzhiyun #define MCFGPIO_PDDR MCFGPIO_PDDR_CS 136*4882a593Smuzhiyun #define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS 137*4882a593Smuzhiyun #define MCFGPIO_SETR MCFGPIO_PPDSDR_CS 138*4882a593Smuzhiyun #define MCFGPIO_CLRR MCFGPIO_PCLRR_CS 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define MCFGPIO_PIN_MAX 80 141*4882a593Smuzhiyun #define MCFGPIO_IRQ_MAX 8 142*4882a593Smuzhiyun #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART 0xFC0A4036 145*4882a593Smuzhiyun #define MCF_GPIO_PAR_FECI2C 0xFC0A4033 146*4882a593Smuzhiyun #define MCF_GPIO_PAR_QSPI 0xFC0A4034 147*4882a593Smuzhiyun #define MCF_GPIO_PAR_FEC 0xFC0A4038 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) 150*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) 153*4882a593Smuzhiyun #define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 156*4882a593Smuzhiyun #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* 159*4882a593Smuzhiyun * PIT timer module. 160*4882a593Smuzhiyun */ 161*4882a593Smuzhiyun #define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */ 162*4882a593Smuzhiyun #define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* 165*4882a593Smuzhiyun * UART module. 166*4882a593Smuzhiyun */ 167*4882a593Smuzhiyun #define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */ 168*4882a593Smuzhiyun #define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */ 169*4882a593Smuzhiyun #define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* 172*4882a593Smuzhiyun * FEC module. 173*4882a593Smuzhiyun */ 174*4882a593Smuzhiyun #define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */ 175*4882a593Smuzhiyun #define MCFFEC_SIZE0 0x800 /* Register set size */ 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* 178*4882a593Smuzhiyun * QSPI module. 179*4882a593Smuzhiyun */ 180*4882a593Smuzhiyun #define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */ 181*4882a593Smuzhiyun #define MCFQSPI_SIZE 0x40 /* Register set size */ 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define MCFQSPI_CS0 46 184*4882a593Smuzhiyun #define MCFQSPI_CS1 47 185*4882a593Smuzhiyun #define MCFQSPI_CS2 27 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* 188*4882a593Smuzhiyun * Reset Control Unit. 189*4882a593Smuzhiyun */ 190*4882a593Smuzhiyun #define MCF_RCR 0xFC0A0000 191*4882a593Smuzhiyun #define MCF_RSR 0xFC0A0001 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 194*4882a593Smuzhiyun #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* 197*4882a593Smuzhiyun * Power Management. 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun #define MCFPM_WCR 0xfc040013 200*4882a593Smuzhiyun #define MCFPM_PPMSR0 0xfc04002c 201*4882a593Smuzhiyun #define MCFPM_PPMCR0 0xfc04002d 202*4882a593Smuzhiyun #define MCFPM_PPMHR0 0xfc040030 203*4882a593Smuzhiyun #define MCFPM_PPMLR0 0xfc040034 204*4882a593Smuzhiyun #define MCFPM_LPCR 0xfc0a0007 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun /* 207*4882a593Smuzhiyun * I2C module. 208*4882a593Smuzhiyun */ 209*4882a593Smuzhiyun #define MCFI2C_BASE0 0xFC058000 210*4882a593Smuzhiyun #define MCFI2C_SIZE0 0x40 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /****************************************************************************/ 213*4882a593Smuzhiyun #endif /* m520xsim_h */ 214