1*4882a593Smuzhiyun|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 2*4882a593Smuzhiyun|MOTOROLA MICROPROCESSOR & MEMORY TECHNOLOGY GROUP 3*4882a593Smuzhiyun|M68000 Hi-Performance Microprocessor Division 4*4882a593Smuzhiyun|M68060 Software Package 5*4882a593Smuzhiyun|Production Release P1.00 -- October 10, 1994 6*4882a593Smuzhiyun| 7*4882a593Smuzhiyun|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved. 8*4882a593Smuzhiyun| 9*4882a593Smuzhiyun|THE SOFTWARE is provided on an "AS IS" basis and without warranty. 10*4882a593Smuzhiyun|To the maximum extent permitted by applicable law, 11*4882a593Smuzhiyun|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, 12*4882a593Smuzhiyun|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE 13*4882a593Smuzhiyun|and any warranty against infringement with regard to the SOFTWARE 14*4882a593Smuzhiyun|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials. 15*4882a593Smuzhiyun| 16*4882a593Smuzhiyun|To the maximum extent permitted by applicable law, 17*4882a593Smuzhiyun|IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER 18*4882a593Smuzhiyun|(INCLUDING WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, 19*4882a593Smuzhiyun|BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) 20*4882a593Smuzhiyun|ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. 21*4882a593Smuzhiyun|Motorola assumes no responsibility for the maintenance and support of the SOFTWARE. 22*4882a593Smuzhiyun| 23*4882a593Smuzhiyun|You are hereby granted a copyright license to use, modify, and distribute the SOFTWARE 24*4882a593Smuzhiyun|so long as this entire notice is retained without alteration in any modified and/or 25*4882a593Smuzhiyun|redistributed versions, and that such modified versions are clearly identified as such. 26*4882a593Smuzhiyun|No licenses are granted by implication, estoppel or otherwise under any patents 27*4882a593Smuzhiyun|or trademarks of Motorola, Inc. 28*4882a593Smuzhiyun|~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 29*4882a593Smuzhiyun| fskeleton.s 30*4882a593Smuzhiyun| 31*4882a593Smuzhiyun| This file contains: 32*4882a593Smuzhiyun| (1) example "Call-out"s 33*4882a593Smuzhiyun| (2) example package entry code 34*4882a593Smuzhiyun| (3) example "Call-out" table 35*4882a593Smuzhiyun| 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun#include <linux/linkage.h> 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun|################################ 40*4882a593Smuzhiyun| (1) EXAMPLE CALL-OUTS # 41*4882a593Smuzhiyun| # 42*4882a593Smuzhiyun| _060_fpsp_done() # 43*4882a593Smuzhiyun| _060_real_ovfl() # 44*4882a593Smuzhiyun| _060_real_unfl() # 45*4882a593Smuzhiyun| _060_real_operr() # 46*4882a593Smuzhiyun| _060_real_snan() # 47*4882a593Smuzhiyun| _060_real_dz() # 48*4882a593Smuzhiyun| _060_real_inex() # 49*4882a593Smuzhiyun| _060_real_bsun() # 50*4882a593Smuzhiyun| _060_real_fline() # 51*4882a593Smuzhiyun| _060_real_fpu_disabled() # 52*4882a593Smuzhiyun| _060_real_trap() # 53*4882a593Smuzhiyun|################################ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun| 56*4882a593Smuzhiyun| _060_fpsp_done(): 57*4882a593Smuzhiyun| 58*4882a593Smuzhiyun| This is the main exit point for the 68060 Floating-Point 59*4882a593Smuzhiyun| Software Package. For a normal exit, all 060FPSP routines call this 60*4882a593Smuzhiyun| routine. The operating system can do system dependent clean-up or 61*4882a593Smuzhiyun| simply execute an "rte" as with the sample code below. 62*4882a593Smuzhiyun| 63*4882a593Smuzhiyun .global _060_fpsp_done 64*4882a593Smuzhiyun_060_fpsp_done: 65*4882a593Smuzhiyun bral _060_isp_done | do the same as isp_done 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun| 68*4882a593Smuzhiyun| _060_real_ovfl(): 69*4882a593Smuzhiyun| 70*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled overflow exception 71*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 72*4882a593Smuzhiyun| for enabled overflow conditions. The exception stack frame is an overflow 73*4882a593Smuzhiyun| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. 74*4882a593Smuzhiyun| 75*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 76*4882a593Smuzhiyun| does an "rte". 77*4882a593Smuzhiyun| 78*4882a593Smuzhiyun .global _060_real_ovfl 79*4882a593Smuzhiyun_060_real_ovfl: 80*4882a593Smuzhiyun fsave -(%sp) 81*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 82*4882a593Smuzhiyun frestore (%sp)+ 83*4882a593Smuzhiyun bral trap | jump to trap handler 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun| 87*4882a593Smuzhiyun| _060_real_unfl(): 88*4882a593Smuzhiyun| 89*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled underflow exception 90*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 91*4882a593Smuzhiyun| for enabled underflow conditions. The exception stack frame is an underflow 92*4882a593Smuzhiyun| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND. 93*4882a593Smuzhiyun| 94*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 95*4882a593Smuzhiyun| does an "rte". 96*4882a593Smuzhiyun| 97*4882a593Smuzhiyun .global _060_real_unfl 98*4882a593Smuzhiyun_060_real_unfl: 99*4882a593Smuzhiyun fsave -(%sp) 100*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 101*4882a593Smuzhiyun frestore (%sp)+ 102*4882a593Smuzhiyun bral trap | jump to trap handler 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun| 105*4882a593Smuzhiyun| _060_real_operr(): 106*4882a593Smuzhiyun| 107*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled operand error exception 108*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 109*4882a593Smuzhiyun| for enabled operand error exceptions. The exception stack frame is an operand error 110*4882a593Smuzhiyun| stack frame. The FP state frame holds the source operand of the faulting 111*4882a593Smuzhiyun| instruction. 112*4882a593Smuzhiyun| 113*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 114*4882a593Smuzhiyun| does an "rte". 115*4882a593Smuzhiyun| 116*4882a593Smuzhiyun .global _060_real_operr 117*4882a593Smuzhiyun_060_real_operr: 118*4882a593Smuzhiyun fsave -(%sp) 119*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 120*4882a593Smuzhiyun frestore (%sp)+ 121*4882a593Smuzhiyun bral trap | jump to trap handler 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun| 124*4882a593Smuzhiyun| _060_real_snan(): 125*4882a593Smuzhiyun| 126*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled signalling NaN exception 127*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 128*4882a593Smuzhiyun| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN 129*4882a593Smuzhiyun| stack frame. The FP state frame holds the source operand of the faulting 130*4882a593Smuzhiyun| instruction. 131*4882a593Smuzhiyun| 132*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 133*4882a593Smuzhiyun| does an "rte". 134*4882a593Smuzhiyun| 135*4882a593Smuzhiyun .global _060_real_snan 136*4882a593Smuzhiyun_060_real_snan: 137*4882a593Smuzhiyun fsave -(%sp) 138*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 139*4882a593Smuzhiyun frestore (%sp)+ 140*4882a593Smuzhiyun bral trap | jump to trap handler 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun| 143*4882a593Smuzhiyun| _060_real_dz(): 144*4882a593Smuzhiyun| 145*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled divide-by-zero exception 146*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 147*4882a593Smuzhiyun| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero 148*4882a593Smuzhiyun| stack frame. The FP state frame holds the source operand of the faulting 149*4882a593Smuzhiyun| instruction. 150*4882a593Smuzhiyun| 151*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 152*4882a593Smuzhiyun| does an "rte". 153*4882a593Smuzhiyun| 154*4882a593Smuzhiyun .global _060_real_dz 155*4882a593Smuzhiyun_060_real_dz: 156*4882a593Smuzhiyun fsave -(%sp) 157*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 158*4882a593Smuzhiyun frestore (%sp)+ 159*4882a593Smuzhiyun bral trap | jump to trap handler 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun| 162*4882a593Smuzhiyun| _060_real_inex(): 163*4882a593Smuzhiyun| 164*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled inexact exception 165*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 166*4882a593Smuzhiyun| for enabled inexact exceptions. The exception stack frame is an inexact 167*4882a593Smuzhiyun| stack frame. The FP state frame holds the source operand of the faulting 168*4882a593Smuzhiyun| instruction. 169*4882a593Smuzhiyun| 170*4882a593Smuzhiyun| The sample routine below simply clears the exception status bit and 171*4882a593Smuzhiyun| does an "rte". 172*4882a593Smuzhiyun| 173*4882a593Smuzhiyun .global _060_real_inex 174*4882a593Smuzhiyun_060_real_inex: 175*4882a593Smuzhiyun fsave -(%sp) 176*4882a593Smuzhiyun move.w #0x6000,0x2(%sp) 177*4882a593Smuzhiyun frestore (%sp)+ 178*4882a593Smuzhiyun bral trap | jump to trap handler 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun| 181*4882a593Smuzhiyun| _060_real_bsun(): 182*4882a593Smuzhiyun| 183*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an enabled bsun exception 184*4882a593Smuzhiyun| is present. The routine below should point to the operating system handler 185*4882a593Smuzhiyun| for enabled bsun exceptions. The exception stack frame is a bsun 186*4882a593Smuzhiyun| stack frame. 187*4882a593Smuzhiyun| 188*4882a593Smuzhiyun| The sample routine below clears the exception status bit, clears the NaN 189*4882a593Smuzhiyun| bit in the FPSR, and does an "rte". The instruction that caused the 190*4882a593Smuzhiyun| bsun will now be re-executed but with the NaN FPSR bit cleared. 191*4882a593Smuzhiyun| 192*4882a593Smuzhiyun .global _060_real_bsun 193*4882a593Smuzhiyun_060_real_bsun: 194*4882a593Smuzhiyun| fsave -(%sp) 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun fmove.l %fpsr,-(%sp) 197*4882a593Smuzhiyun andi.b #0xfe,(%sp) 198*4882a593Smuzhiyun fmove.l (%sp)+,%fpsr 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun bral trap | jump to trap handler 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun| 203*4882a593Smuzhiyun| _060_real_fline(): 204*4882a593Smuzhiyun| 205*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an F-Line Illegal exception is 206*4882a593Smuzhiyun| encountered. Three different types of exceptions can enter the F-Line exception 207*4882a593Smuzhiyun| vector number 11: FP Unimplemented Instructions, FP implemented instructions when 208*4882a593Smuzhiyun| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module 209*4882a593Smuzhiyun| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line 210*4882a593Smuzhiyun| Illegals branch here. 211*4882a593Smuzhiyun| 212*4882a593Smuzhiyun .global _060_real_fline 213*4882a593Smuzhiyun_060_real_fline: 214*4882a593Smuzhiyun bral trap | jump to trap handler 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun| 217*4882a593Smuzhiyun| _060_real_fpu_disabled(): 218*4882a593Smuzhiyun| 219*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an FPU disabled exception is 220*4882a593Smuzhiyun| encountered. Three different types of exceptions can enter the F-Line exception 221*4882a593Smuzhiyun| vector number 11: FP Unimplemented Instructions, FP implemented instructions when 222*4882a593Smuzhiyun| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module 223*4882a593Smuzhiyun| _fpsp_fline() distinguishes between the three and acts appropriately. FPU disabled 224*4882a593Smuzhiyun| exceptions branch here. 225*4882a593Smuzhiyun| 226*4882a593Smuzhiyun| The sample code below enables the FPU, sets the PC field in the exception stack 227*4882a593Smuzhiyun| frame to the PC of the instruction causing the exception, and does an "rte". 228*4882a593Smuzhiyun| The execution of the instruction then proceeds with an enabled floating-point 229*4882a593Smuzhiyun| unit. 230*4882a593Smuzhiyun| 231*4882a593Smuzhiyun .global _060_real_fpu_disabled 232*4882a593Smuzhiyun_060_real_fpu_disabled: 233*4882a593Smuzhiyun move.l %d0,-(%sp) | enabled the fpu 234*4882a593Smuzhiyun .long 0x4E7A0808 |movec pcr,%d0 235*4882a593Smuzhiyun bclr #0x1,%d0 236*4882a593Smuzhiyun .long 0x4E7B0808 |movec %d0,pcr 237*4882a593Smuzhiyun move.l (%sp)+,%d0 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun move.l 0xc(%sp),0x2(%sp) | set "Current PC" 240*4882a593Smuzhiyun rte 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun| 243*4882a593Smuzhiyun| _060_real_trap(): 244*4882a593Smuzhiyun| 245*4882a593Smuzhiyun| This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction 246*4882a593Smuzhiyun| discovers that the trap condition is true and it should branch to the operating 247*4882a593Smuzhiyun| system handler for the trap exception vector number 7. 248*4882a593Smuzhiyun| 249*4882a593Smuzhiyun| The sample code below simply executes an "rte". 250*4882a593Smuzhiyun| 251*4882a593Smuzhiyun .global _060_real_trap 252*4882a593Smuzhiyun_060_real_trap: 253*4882a593Smuzhiyun bral trap | jump to trap handler 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun|############################################################################ 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun|################################# 258*4882a593Smuzhiyun| (2) EXAMPLE PACKAGE ENTRY CODE # 259*4882a593Smuzhiyun|################################# 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun .global _060_fpsp_snan 262*4882a593Smuzhiyun_060_fpsp_snan: 263*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x00 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun .global _060_fpsp_operr 266*4882a593Smuzhiyun_060_fpsp_operr: 267*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x08 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun .global _060_fpsp_ovfl 270*4882a593Smuzhiyun_060_fpsp_ovfl: 271*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x10 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun .global _060_fpsp_unfl 274*4882a593Smuzhiyun_060_fpsp_unfl: 275*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x18 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun .global _060_fpsp_dz 278*4882a593Smuzhiyun_060_fpsp_dz: 279*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x20 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun .global _060_fpsp_inex 282*4882a593Smuzhiyun_060_fpsp_inex: 283*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x28 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun .global _060_fpsp_fline 286*4882a593Smuzhiyun_060_fpsp_fline: 287*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x30 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun .global _060_fpsp_unsupp 290*4882a593Smuzhiyun_060_fpsp_unsupp: 291*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x38 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun .global _060_fpsp_effadd 294*4882a593Smuzhiyun_060_fpsp_effadd: 295*4882a593Smuzhiyun bra.l _FP_CALL_TOP+0x80+0x40 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun|############################################################################ 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun|############################### 300*4882a593Smuzhiyun| (3) EXAMPLE CALL-OUT SECTION # 301*4882a593Smuzhiyun|############################### 302*4882a593Smuzhiyun 303*4882a593Smuzhiyun| The size of this section MUST be 128 bytes!!! 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun_FP_CALL_TOP: 306*4882a593Smuzhiyun .long _060_real_bsun - _FP_CALL_TOP 307*4882a593Smuzhiyun .long _060_real_snan - _FP_CALL_TOP 308*4882a593Smuzhiyun .long _060_real_operr - _FP_CALL_TOP 309*4882a593Smuzhiyun .long _060_real_ovfl - _FP_CALL_TOP 310*4882a593Smuzhiyun .long _060_real_unfl - _FP_CALL_TOP 311*4882a593Smuzhiyun .long _060_real_dz - _FP_CALL_TOP 312*4882a593Smuzhiyun .long _060_real_inex - _FP_CALL_TOP 313*4882a593Smuzhiyun .long _060_real_fline - _FP_CALL_TOP 314*4882a593Smuzhiyun .long _060_real_fpu_disabled - _FP_CALL_TOP 315*4882a593Smuzhiyun .long _060_real_trap - _FP_CALL_TOP 316*4882a593Smuzhiyun .long _060_real_trace - _FP_CALL_TOP 317*4882a593Smuzhiyun .long _060_real_access - _FP_CALL_TOP 318*4882a593Smuzhiyun .long _060_fpsp_done - _FP_CALL_TOP 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun .long 0x00000000, 0x00000000, 0x00000000 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun .long _060_imem_read - _FP_CALL_TOP 323*4882a593Smuzhiyun .long _060_dmem_read - _FP_CALL_TOP 324*4882a593Smuzhiyun .long _060_dmem_write - _FP_CALL_TOP 325*4882a593Smuzhiyun .long _060_imem_read_word - _FP_CALL_TOP 326*4882a593Smuzhiyun .long _060_imem_read_long - _FP_CALL_TOP 327*4882a593Smuzhiyun .long _060_dmem_read_byte - _FP_CALL_TOP 328*4882a593Smuzhiyun .long _060_dmem_read_word - _FP_CALL_TOP 329*4882a593Smuzhiyun .long _060_dmem_read_long - _FP_CALL_TOP 330*4882a593Smuzhiyun .long _060_dmem_write_byte - _FP_CALL_TOP 331*4882a593Smuzhiyun .long _060_dmem_write_word - _FP_CALL_TOP 332*4882a593Smuzhiyun .long _060_dmem_write_long - _FP_CALL_TOP 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun .long 0x00000000 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun .long 0x00000000, 0x00000000, 0x00000000, 0x00000000 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun|############################################################################ 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun| 060 FPSP KERNEL PACKAGE NEEDS TO GO HERE!!! 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun#include "fpsp.sa" 343