1*4882a593Smuzhiyun| 2*4882a593Smuzhiyun| sto_res.sa 3.1 12/10/90 3*4882a593Smuzhiyun| 4*4882a593Smuzhiyun| Takes the result and puts it in where the user expects it. 5*4882a593Smuzhiyun| Library functions return result in fp0. If fp0 is not the 6*4882a593Smuzhiyun| users destination register then fp0 is moved to the 7*4882a593Smuzhiyun| correct floating-point destination register. fp0 and fp1 8*4882a593Smuzhiyun| are then restored to the original contents. 9*4882a593Smuzhiyun| 10*4882a593Smuzhiyun| Input: result in fp0,fp1 11*4882a593Smuzhiyun| 12*4882a593Smuzhiyun| d2 & a0 should be kept unmodified 13*4882a593Smuzhiyun| 14*4882a593Smuzhiyun| Output: moves the result to the true destination reg or mem 15*4882a593Smuzhiyun| 16*4882a593Smuzhiyun| Modifies: destination floating point register 17*4882a593Smuzhiyun| 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun| Copyright (C) Motorola, Inc. 1990 20*4882a593Smuzhiyun| All Rights Reserved 21*4882a593Smuzhiyun| 22*4882a593Smuzhiyun| For details on the license for this file, please see the 23*4882a593Smuzhiyun| file, README, in this same directory. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunSTO_RES: |idnt 2,1 | Motorola 040 Floating Point Software Package 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun |section 8 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun#include "fpsp.h" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun .global sto_cos 33*4882a593Smuzhiyunsto_cos: 34*4882a593Smuzhiyun bfextu CMDREG1B(%a6){#13:#3},%d0 |extract cos destination 35*4882a593Smuzhiyun cmpib #3,%d0 |check for fp0/fp1 cases 36*4882a593Smuzhiyun bles c_fp0123 37*4882a593Smuzhiyun fmovemx %fp1-%fp1,-(%a7) 38*4882a593Smuzhiyun moveql #7,%d1 39*4882a593Smuzhiyun subl %d0,%d1 |d1 = 7- (dest. reg. no.) 40*4882a593Smuzhiyun clrl %d0 41*4882a593Smuzhiyun bsetl %d1,%d0 |d0 is dynamic register mask 42*4882a593Smuzhiyun fmovemx (%a7)+,%d0 43*4882a593Smuzhiyun rts 44*4882a593Smuzhiyunc_fp0123: 45*4882a593Smuzhiyun cmpib #0,%d0 46*4882a593Smuzhiyun beqs c_is_fp0 47*4882a593Smuzhiyun cmpib #1,%d0 48*4882a593Smuzhiyun beqs c_is_fp1 49*4882a593Smuzhiyun cmpib #2,%d0 50*4882a593Smuzhiyun beqs c_is_fp2 51*4882a593Smuzhiyunc_is_fp3: 52*4882a593Smuzhiyun fmovemx %fp1-%fp1,USER_FP3(%a6) 53*4882a593Smuzhiyun rts 54*4882a593Smuzhiyunc_is_fp2: 55*4882a593Smuzhiyun fmovemx %fp1-%fp1,USER_FP2(%a6) 56*4882a593Smuzhiyun rts 57*4882a593Smuzhiyunc_is_fp1: 58*4882a593Smuzhiyun fmovemx %fp1-%fp1,USER_FP1(%a6) 59*4882a593Smuzhiyun rts 60*4882a593Smuzhiyunc_is_fp0: 61*4882a593Smuzhiyun fmovemx %fp1-%fp1,USER_FP0(%a6) 62*4882a593Smuzhiyun rts 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun .global sto_res 66*4882a593Smuzhiyunsto_res: 67*4882a593Smuzhiyun bfextu CMDREG1B(%a6){#6:#3},%d0 |extract destination register 68*4882a593Smuzhiyun cmpib #3,%d0 |check for fp0/fp1 cases 69*4882a593Smuzhiyun bles fp0123 70*4882a593Smuzhiyun fmovemx %fp0-%fp0,-(%a7) 71*4882a593Smuzhiyun moveql #7,%d1 72*4882a593Smuzhiyun subl %d0,%d1 |d1 = 7- (dest. reg. no.) 73*4882a593Smuzhiyun clrl %d0 74*4882a593Smuzhiyun bsetl %d1,%d0 |d0 is dynamic register mask 75*4882a593Smuzhiyun fmovemx (%a7)+,%d0 76*4882a593Smuzhiyun rts 77*4882a593Smuzhiyunfp0123: 78*4882a593Smuzhiyun cmpib #0,%d0 79*4882a593Smuzhiyun beqs is_fp0 80*4882a593Smuzhiyun cmpib #1,%d0 81*4882a593Smuzhiyun beqs is_fp1 82*4882a593Smuzhiyun cmpib #2,%d0 83*4882a593Smuzhiyun beqs is_fp2 84*4882a593Smuzhiyunis_fp3: 85*4882a593Smuzhiyun fmovemx %fp0-%fp0,USER_FP3(%a6) 86*4882a593Smuzhiyun rts 87*4882a593Smuzhiyunis_fp2: 88*4882a593Smuzhiyun fmovemx %fp0-%fp0,USER_FP2(%a6) 89*4882a593Smuzhiyun rts 90*4882a593Smuzhiyunis_fp1: 91*4882a593Smuzhiyun fmovemx %fp0-%fp0,USER_FP1(%a6) 92*4882a593Smuzhiyun rts 93*4882a593Smuzhiyunis_fp0: 94*4882a593Smuzhiyun fmovemx %fp0-%fp0,USER_FP0(%a6) 95*4882a593Smuzhiyun rts 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun |end 98