1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * stmark2.c -- Support for Sysam AMCORE open board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is subject to the terms and conditions of the GNU General Public
7*4882a593Smuzhiyun * License. See the file COPYING in the main directory of this archive
8*4882a593Smuzhiyun * for more details.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/mtd/partitions.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun #include <linux/spi/spi-fsl-dspi.h>
15*4882a593Smuzhiyun #include <linux/spi/flash.h>
16*4882a593Smuzhiyun #include <linux/dma-mapping.h>
17*4882a593Smuzhiyun #include <asm/mcfsim.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Partitioning of parallel NOR flash (39VF3201B)
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun static struct mtd_partition stmark2_partitions[] = {
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun .name = "U-Boot (1024K)",
25*4882a593Smuzhiyun .size = 0x100000,
26*4882a593Smuzhiyun .offset = 0x0
27*4882a593Smuzhiyun }, {
28*4882a593Smuzhiyun .name = "Kernel+initramfs (7168K)",
29*4882a593Smuzhiyun .size = 0x700000,
30*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND
31*4882a593Smuzhiyun }, {
32*4882a593Smuzhiyun .name = "Flash Free Space (8192K)",
33*4882a593Smuzhiyun .size = MTDPART_SIZ_FULL,
34*4882a593Smuzhiyun .offset = MTDPART_OFS_APPEND
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static struct flash_platform_data stmark2_spi_flash_data = {
39*4882a593Smuzhiyun .name = "is25lp128",
40*4882a593Smuzhiyun .parts = stmark2_partitions,
41*4882a593Smuzhiyun .nr_parts = ARRAY_SIZE(stmark2_partitions),
42*4882a593Smuzhiyun .type = "is25lp128",
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static struct spi_board_info stmark2_board_info[] __initdata = {
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun .modalias = "m25p80",
48*4882a593Smuzhiyun .max_speed_hz = 5000000,
49*4882a593Smuzhiyun .bus_num = 0,
50*4882a593Smuzhiyun .chip_select = 1,
51*4882a593Smuzhiyun .platform_data = &stmark2_spi_flash_data,
52*4882a593Smuzhiyun .mode = SPI_MODE_3,
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /* SPI controller data, SPI (0) */
57*4882a593Smuzhiyun static struct fsl_dspi_platform_data dspi_spi0_info = {
58*4882a593Smuzhiyun .cs_num = 4,
59*4882a593Smuzhiyun .bus_num = 0,
60*4882a593Smuzhiyun .sck_cs_delay = 100,
61*4882a593Smuzhiyun .cs_sck_delay = 100,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static struct resource dspi_spi0_resource[] = {
65*4882a593Smuzhiyun [0] = {
66*4882a593Smuzhiyun .start = MCFDSPI_BASE0,
67*4882a593Smuzhiyun .end = MCFDSPI_BASE0 + 0xFF,
68*4882a593Smuzhiyun .flags = IORESOURCE_MEM,
69*4882a593Smuzhiyun },
70*4882a593Smuzhiyun [1] = {
71*4882a593Smuzhiyun .start = 12,
72*4882a593Smuzhiyun .end = 13,
73*4882a593Smuzhiyun .flags = IORESOURCE_DMA,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun [2] = {
76*4882a593Smuzhiyun .start = MCF_IRQ_DSPI0,
77*4882a593Smuzhiyun .end = MCF_IRQ_DSPI0,
78*4882a593Smuzhiyun .flags = IORESOURCE_IRQ,
79*4882a593Smuzhiyun },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static u64 stmark2_dspi_mask = DMA_BIT_MASK(32);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* SPI controller, id = bus number */
85*4882a593Smuzhiyun static struct platform_device dspi_spi0_device = {
86*4882a593Smuzhiyun .name = "fsl-dspi",
87*4882a593Smuzhiyun .id = 0,
88*4882a593Smuzhiyun .num_resources = ARRAY_SIZE(dspi_spi0_resource),
89*4882a593Smuzhiyun .resource = dspi_spi0_resource,
90*4882a593Smuzhiyun .dev = {
91*4882a593Smuzhiyun .platform_data = &dspi_spi0_info,
92*4882a593Smuzhiyun .dma_mask = &stmark2_dspi_mask,
93*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun static struct platform_device *stmark2_devices[] __initdata = {
98*4882a593Smuzhiyun &dspi_spi0_device,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * Note: proper pin-mux setup is mandatory for proper SPI functionality.
103*4882a593Smuzhiyun */
init_stmark2(void)104*4882a593Smuzhiyun static int __init init_stmark2(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun /* DSPI0, all pins as DSPI, and using CS1 */
107*4882a593Smuzhiyun __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
108*4882a593Smuzhiyun __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* Board gpio setup */
111*4882a593Smuzhiyun __raw_writeb(0x00, MCFGPIO_PAR_BE);
112*4882a593Smuzhiyun __raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
113*4882a593Smuzhiyun __raw_writeb(0x00, MCFGPIO_PAR_CS);
114*4882a593Smuzhiyun __raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun spi_register_board_info(stmark2_board_info,
119*4882a593Smuzhiyun ARRAY_SIZE(stmark2_board_info));
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun late_initcall(init_stmark2);
125