1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * sltimers.c -- generic ColdFire slice timer support.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
8*4882a593Smuzhiyun * based on
9*4882a593Smuzhiyun * timers.c -- generic ColdFire hardware timer support.
10*4882a593Smuzhiyun * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /***************************************************************************/
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/sched.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/irq.h>
20*4882a593Smuzhiyun #include <linux/profile.h>
21*4882a593Smuzhiyun #include <linux/clocksource.h>
22*4882a593Smuzhiyun #include <asm/io.h>
23*4882a593Smuzhiyun #include <asm/traps.h>
24*4882a593Smuzhiyun #include <asm/machdep.h>
25*4882a593Smuzhiyun #include <asm/coldfire.h>
26*4882a593Smuzhiyun #include <asm/mcfslt.h>
27*4882a593Smuzhiyun #include <asm/mcfsim.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /***************************************************************************/
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #ifdef CONFIG_HIGHPROFILE
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun * By default use Slice Timer 1 as the profiler clock timer.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun #define PA(a) (MCFSLT_TIMER1 + (a))
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * Choose a reasonably fast profile timer. Make it an odd value to
40*4882a593Smuzhiyun * try and get good coverage of kernel operations.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun #define PROFILEHZ 1013
43*4882a593Smuzhiyun
mcfslt_profile_tick(int irq,void * dummy)44*4882a593Smuzhiyun irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun /* Reset Slice Timer 1 */
47*4882a593Smuzhiyun __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
48*4882a593Smuzhiyun if (current->pid)
49*4882a593Smuzhiyun profile_tick(CPU_PROFILING);
50*4882a593Smuzhiyun return IRQ_HANDLED;
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
mcfslt_profile_init(void)53*4882a593Smuzhiyun void mcfslt_profile_init(void)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun int ret;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
58*4882a593Smuzhiyun PROFILEHZ);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER,
61*4882a593Smuzhiyun "profile timer", NULL);
62*4882a593Smuzhiyun if (ret) {
63*4882a593Smuzhiyun pr_err("Failed to request irq %d (profile timer): %pe\n",
64*4882a593Smuzhiyun MCF_IRQ_PROFILER, ERR_PTR(ret));
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Set up TIMER 2 as high speed profile clock */
68*4882a593Smuzhiyun __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
69*4882a593Smuzhiyun __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
70*4882a593Smuzhiyun PA(MCFSLT_SCR));
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #endif /* CONFIG_HIGHPROFILE */
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /***************************************************************************/
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /*
79*4882a593Smuzhiyun * By default use Slice Timer 0 as the system clock timer.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun #define TA(a) (MCFSLT_TIMER0 + (a))
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static u32 mcfslt_cycles_per_jiffy;
84*4882a593Smuzhiyun static u32 mcfslt_cnt;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static irq_handler_t timer_interrupt;
87*4882a593Smuzhiyun
mcfslt_tick(int irq,void * dummy)88*4882a593Smuzhiyun static irqreturn_t mcfslt_tick(int irq, void *dummy)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun /* Reset Slice Timer 0 */
91*4882a593Smuzhiyun __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
92*4882a593Smuzhiyun mcfslt_cnt += mcfslt_cycles_per_jiffy;
93*4882a593Smuzhiyun return timer_interrupt(irq, dummy);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
mcfslt_read_clk(struct clocksource * cs)96*4882a593Smuzhiyun static u64 mcfslt_read_clk(struct clocksource *cs)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun unsigned long flags;
99*4882a593Smuzhiyun u32 cycles, scnt;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun local_irq_save(flags);
102*4882a593Smuzhiyun scnt = __raw_readl(TA(MCFSLT_SCNT));
103*4882a593Smuzhiyun cycles = mcfslt_cnt;
104*4882a593Smuzhiyun if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
105*4882a593Smuzhiyun cycles += mcfslt_cycles_per_jiffy;
106*4882a593Smuzhiyun scnt = __raw_readl(TA(MCFSLT_SCNT));
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun local_irq_restore(flags);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* subtract because slice timers count down */
111*4882a593Smuzhiyun return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static struct clocksource mcfslt_clk = {
115*4882a593Smuzhiyun .name = "slt",
116*4882a593Smuzhiyun .rating = 250,
117*4882a593Smuzhiyun .read = mcfslt_read_clk,
118*4882a593Smuzhiyun .mask = CLOCKSOURCE_MASK(32),
119*4882a593Smuzhiyun .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
hw_timer_init(irq_handler_t handler)122*4882a593Smuzhiyun void hw_timer_init(irq_handler_t handler)
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun int r;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
127*4882a593Smuzhiyun /*
128*4882a593Smuzhiyun * The coldfire slice timer (SLT) runs from STCNT to 0 included,
129*4882a593Smuzhiyun * then STCNT again and so on. It counts thus actually
130*4882a593Smuzhiyun * STCNT + 1 steps for 1 tick, not STCNT. So if you want
131*4882a593Smuzhiyun * n cycles, initialize STCNT with n - 1.
132*4882a593Smuzhiyun */
133*4882a593Smuzhiyun __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
134*4882a593Smuzhiyun __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
135*4882a593Smuzhiyun TA(MCFSLT_SCR));
136*4882a593Smuzhiyun /* initialize mcfslt_cnt knowing that slice timers count down */
137*4882a593Smuzhiyun mcfslt_cnt = mcfslt_cycles_per_jiffy;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun timer_interrupt = handler;
140*4882a593Smuzhiyun r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL);
141*4882a593Smuzhiyun if (r) {
142*4882a593Smuzhiyun pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
143*4882a593Smuzhiyun ERR_PTR(r));
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun #ifdef CONFIG_HIGHPROFILE
149*4882a593Smuzhiyun mcfslt_profile_init();
150*4882a593Smuzhiyun #endif
151*4882a593Smuzhiyun }
152