1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m54xx.c -- platform support for ColdFire 54xx based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /***************************************************************************/
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/param.h>
14*4882a593Smuzhiyun #include <linux/init.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <linux/mm.h>
18*4882a593Smuzhiyun #include <linux/clk.h>
19*4882a593Smuzhiyun #include <linux/memblock.h>
20*4882a593Smuzhiyun #include <asm/pgalloc.h>
21*4882a593Smuzhiyun #include <asm/machdep.h>
22*4882a593Smuzhiyun #include <asm/coldfire.h>
23*4882a593Smuzhiyun #include <asm/m54xxsim.h>
24*4882a593Smuzhiyun #include <asm/mcfuart.h>
25*4882a593Smuzhiyun #include <asm/mcfclk.h>
26*4882a593Smuzhiyun #include <asm/m54xxgpt.h>
27*4882a593Smuzhiyun #ifdef CONFIG_MMU
28*4882a593Smuzhiyun #include <asm/mmu_context.h>
29*4882a593Smuzhiyun #endif
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /***************************************************************************/
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
34*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
35*4882a593Smuzhiyun DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
36*4882a593Smuzhiyun DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
39*4882a593Smuzhiyun DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
40*4882a593Smuzhiyun DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
41*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct clk *mcf_clks[] = {
44*4882a593Smuzhiyun &clk_pll,
45*4882a593Smuzhiyun &clk_sys,
46*4882a593Smuzhiyun &clk_mcfslt0,
47*4882a593Smuzhiyun &clk_mcfslt1,
48*4882a593Smuzhiyun &clk_mcfuart0,
49*4882a593Smuzhiyun &clk_mcfuart1,
50*4882a593Smuzhiyun &clk_mcfuart2,
51*4882a593Smuzhiyun &clk_mcfuart3,
52*4882a593Smuzhiyun &clk_mcfi2c0,
53*4882a593Smuzhiyun NULL
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /***************************************************************************/
57*4882a593Smuzhiyun
m54xx_uarts_init(void)58*4882a593Smuzhiyun static void __init m54xx_uarts_init(void)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun /* enable io pins */
61*4882a593Smuzhiyun __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
62*4882a593Smuzhiyun __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
63*4882a593Smuzhiyun MCFGPIO_PAR_PSC1);
64*4882a593Smuzhiyun __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
65*4882a593Smuzhiyun MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
66*4882a593Smuzhiyun __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /***************************************************************************/
70*4882a593Smuzhiyun
m54xx_i2c_init(void)71*4882a593Smuzhiyun static void __init m54xx_i2c_init(void)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
74*4882a593Smuzhiyun u32 r;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* set the fec/i2c/irq pin assignment register for i2c */
77*4882a593Smuzhiyun r = readl(MCF_PAR_FECI2CIRQ);
78*4882a593Smuzhiyun r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
79*4882a593Smuzhiyun writel(r, MCF_PAR_FECI2CIRQ);
80*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /***************************************************************************/
84*4882a593Smuzhiyun
mcf54xx_reset(void)85*4882a593Smuzhiyun static void mcf54xx_reset(void)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun /* disable interrupts and enable the watchdog */
88*4882a593Smuzhiyun asm("movew #0x2700, %sr\n");
89*4882a593Smuzhiyun __raw_writel(0, MCF_GPT_GMS0);
90*4882a593Smuzhiyun __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
91*4882a593Smuzhiyun __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
92*4882a593Smuzhiyun MCF_GPT_GMS0);
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun /***************************************************************************/
96*4882a593Smuzhiyun
config_BSP(char * commandp,int size)97*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun mach_reset = mcf54xx_reset;
100*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
101*4882a593Smuzhiyun m54xx_uarts_init();
102*4882a593Smuzhiyun m54xx_i2c_init();
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /***************************************************************************/
106