1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /***************************************************************************/
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun /*
5*4882a593Smuzhiyun * m5307.c -- platform support for ColdFire 5307 based boards
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
8*4882a593Smuzhiyun * Copyright (C) 2000, Lineo (www.lineo.com)
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun /***************************************************************************/
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/param.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/io.h>
17*4882a593Smuzhiyun #include <asm/machdep.h>
18*4882a593Smuzhiyun #include <asm/coldfire.h>
19*4882a593Smuzhiyun #include <asm/mcfsim.h>
20*4882a593Smuzhiyun #include <asm/mcfwdebug.h>
21*4882a593Smuzhiyun #include <asm/mcfclk.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /***************************************************************************/
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * Some platforms need software versions of the GPIO data registers.
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun unsigned short ppdata;
29*4882a593Smuzhiyun unsigned char ledbank = 0xff;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /***************************************************************************/
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun DEFINE_CLK(pll, "pll.0", MCF_CLK);
34*4882a593Smuzhiyun DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
35*4882a593Smuzhiyun DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
36*4882a593Smuzhiyun DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
37*4882a593Smuzhiyun DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
38*4882a593Smuzhiyun DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
39*4882a593Smuzhiyun DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct clk *mcf_clks[] = {
42*4882a593Smuzhiyun &clk_pll,
43*4882a593Smuzhiyun &clk_sys,
44*4882a593Smuzhiyun &clk_mcftmr0,
45*4882a593Smuzhiyun &clk_mcftmr1,
46*4882a593Smuzhiyun &clk_mcfuart0,
47*4882a593Smuzhiyun &clk_mcfuart1,
48*4882a593Smuzhiyun &clk_mcfi2c0,
49*4882a593Smuzhiyun NULL
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /***************************************************************************/
53*4882a593Smuzhiyun
m5307_i2c_init(void)54*4882a593Smuzhiyun static void __init m5307_i2c_init(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C_IMX)
57*4882a593Smuzhiyun writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
58*4882a593Smuzhiyun MCFSIM_I2CICR);
59*4882a593Smuzhiyun mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
60*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /***************************************************************************/
64*4882a593Smuzhiyun
config_BSP(char * commandp,int size)65*4882a593Smuzhiyun void __init config_BSP(char *commandp, int size)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun #if defined(CONFIG_NETtel) || \
68*4882a593Smuzhiyun defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
69*4882a593Smuzhiyun /* Copy command line from FLASH to local buffer... */
70*4882a593Smuzhiyun memcpy(commandp, (char *) 0xf0004000, size);
71*4882a593Smuzhiyun commandp[size-1] = 0;
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun mach_sched_init = hw_timer_init;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Only support the external interrupts on their primary level */
77*4882a593Smuzhiyun mcf_mapirq2imr(25, MCFINTC_EINT1);
78*4882a593Smuzhiyun mcf_mapirq2imr(27, MCFINTC_EINT3);
79*4882a593Smuzhiyun mcf_mapirq2imr(29, MCFINTC_EINT5);
80*4882a593Smuzhiyun mcf_mapirq2imr(31, MCFINTC_EINT7);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #ifdef CONFIG_BDM_DISABLE
83*4882a593Smuzhiyun /*
84*4882a593Smuzhiyun * Disable the BDM clocking. This also turns off most of the rest of
85*4882a593Smuzhiyun * the BDM device. This is good for EMC reasons. This option is not
86*4882a593Smuzhiyun * incompatible with the memory protection option.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun m5307_i2c_init();
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /***************************************************************************/
94